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[AXI dv Plan]: Minor feedback #2065

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ludovicpion opened this issue Apr 22, 2024 · 4 comments
Closed
1 task done

[AXI dv Plan]: Minor feedback #2065

ludovicpion opened this issue Apr 22, 2024 · 4 comments
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Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@ludovicpion
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Is there an existing CVA6 bug for this?

  • I have searched the existing bug issues

Bug Description

Hi,
As agreed, we (CEA) hae reviewed the AXI dv_plan. Only minor points to highlight.

Item: 013
• XLEN is not mentioned in the specification. Do we have to understand the XLEN= AXI DATA WIDTH ?

Item: 014
In the dvPlan: ARSIZE can not be equal to 3 if ARID = 1
but in the spec: if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1.
=> So the ARLEN = 0 condition is missing in the dvplan

In the dvPlan: ARSIZE can not be equal to 0, 1 or 2 if ARLOCK = 1
but in the spec if(RVA) AxLOCK = 1 => AxSIZE > 1.
=> Should be
ARSIZE can not be equal to 0 or 1 if ARLOCK = 1 (already present in the Item: 015)
ARSIZE is equal to 2 if ARLOCK = 1

Regards,
Ludovic

@ludovicpion ludovicpion added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Apr 22, 2024
@JeanRochCoulon
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Thank you @ludovicpion for this feedback

@ludovicpion
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Hi,

As far as I can see the comment on items 14 is still valid:

tem: 014
In the dvPlan: ARSIZE can not be equal to 3 if ARID = 1
but in the spec: if(RV32) ARSIZE != 3 && ARLEN = 0 && ARID = 1.
=> So the ARLEN = 0 condition is missing in the dvplan

In the dvPlan: ARSIZE can not be equal to 0, 1 or 2 if ARLOCK = 1
but in the spec if(RVA) AxLOCK = 1 => AxSIZE > 1.
=> Should be
ARSIZE can not be equal to 0 or 1 if ARLOCK = 1 (already present in the Item: 015)
ARSIZE is equal to 2 if ARLOCK = 1

Regards,
Ludovic

@JeanRochCoulon
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@AEzzejjari Do you confirm the feedbacks are inserted in the doc ? If ok, the issue can be closed.

@AEzzejjari
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Yes I do

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Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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