Steps to run bare metal code on implemented CVA6 core

[yadu-kr]

Hello,

I'm currently working with a ZCU102 FPGA board. Due to some dependencies, I'm forced to work with an older version of CVA6, which is based primarily on v4.0.0. I have managed to synthesise all the components except the SPI interface (SD card) and the Ethernet, implement them, and generate the bitstream successfully. I'm now stuck on how to get some bare-metal instructions running on the processor and debugging it possibly by outputting some data via UART to a console.

As far as I've managed to understand, the RTL contains a ZSBL (bootrom.sv) which is invoked first, and this points to the base of the DRAM which contains the FSBL. I don't understand this boot process and the components involved clearly. Where is this DRAM located? The FSBL is then said to boot from SD card by default, but since I don't have the SPI interface available, how would I proceed?

Would appreciate any help, thanks!