Illegal instruction at start of ram during Questa simulation

[artakarakelyan]

I'm using the branch release/v4.3.0 assuming it is stable

Trying to run simulation with Questa using one of tests

make sim elf-bin=./tmp/riscv-tests/build/share/riscv-tests/isa/rv64ui-p-add batch-mode=1

After jumping to ram start 0x80000000 the core introduces illegal instruction and jumps to 0x10040

Verilator simulation looks ok

Questa version is 2022.04
I guess the elf does not load into ram and it contains all 0s.

Here is the simulation log

5470ns      266 M 0000000000010000 0 00100413 li             s0, 1                 s0  :0000000000000001
5570ns      271 M 0000000000010004 0 01f41413 slli           s0, s0, 0x1f          s0  :0000000080000000 s0  :0000000000000001
5670ns      276 M 0000000000010008 0 f1402573 csrr           a0, mhartid           a0  :0000000000000000
5770ns      281 M 000000000001000c 0 00000597 auipc          a1, 0x0               a1  :000000000001000c
5870ns      286 M 0000000000010010 0 07458593 addi           a1, a1, 116           a1  :0000000000010080 a1  :000000000001000c
5970ns      291 M 0000000000010014 1 00040067 jalr           x0, s0, 0             s0  :0000000080000000
Exception @      6170, PC: 0000000080000000, Cause: Illegal Instruction, 
                            tval: 0000000000000000
6370ns      311 M 0000000000010040 0 f1402573 csrr           a0, mhartid           a0  :0000000000000000
6470ns      316 M 0000000000010044 0 00000597 auipc          a1, 0x0               a1  :0000000000010044
6570ns      321 M 0000000000010048 0 03c58593 addi           a1, a1, 60            a1  :0000000000010080 a1  :0000000000010044

[niwis]

Hello @artakarakelyan, this is expected. The simulation starts with an empty RAM. After a while, the frontend-server should connect via the debug module, load the program via JTAG, and start execution. Perhaps wait a bit longer for this to happen.

[artakarakelyan]

Hi Nils,

The simulation runs up to the $finish call. I guess the processor shall be halted until the ram gets loaded with code. but it runs over empty ram until $finish is called. I have tried the hello.elf example with pk described in Readme.md as well. The same behavior.
If the Readme.md is outdated, could you please describe how the simulation shall be run with Questa ?

[artakarakelyan]

On 4.2.0 tag the simulation works. I guess there was some discrepancy between code and riscv-tools