Enhancement: Expand ARM SVE support in jit_uni_batch_normalization

[nikhilfujitsu]

Description

This commit enhances the existing ARM SVE support in jit_uni_batch_normalization to include additional vector length compatibility. The changes made are for implementation of multiple ISAs.

Major Code changes:

• Updated the block size definition to accommodate different ISAs.
• Added 'OR' conditions to extend support for additonal block_size.
• Predicate registers are set according to isa vector length.
• ldr and str instruction changed to ldw1 and stw1 respectively. To support load and store operations as per ISA.

Checklist

General
[✓] Do all unit and benchdnn tests (make test and make test_benchdnn_*) pass locally for each commit? Yes
Test output is same with and without this commit.

make test output:
99% tests passed, 1 tests failed out of 103

Total Test time (real) = 36.37 sec

The following tests FAILED:
102 - test_graph_unit_cpu (Failed)
Errors while running CTest
Output from these tests are in: /home/nikhil/TEST/oneDNN/build/Testing/Temporary/LastTest.log
Use "--rerun-failed --output-on-failure" to re-run the failed cases verbosely.
make: *** [Makefile:71: test] Error 8

make test_benchdnn_* output:
make: *** No rule to make target 'test_benchdnn_*'. Stop.

make test_benchdnn_bnorm_ci_cpu/fast output.
tests:4445 passed:1232 skipped:2989 mistrusted:224 unimplemented:0 invalid_arguments:0 failed:0 listed:0

[mgouicem]

Thanks for the PR @nikhilfujitsu .

• src/cpu/aarch64/jit_uni_batch_normalization.cpp is failing code formatting. Could you please run clang format on your changeset?
• could you squash your commits and name the commit following oneDNN commit message guideline (https://github.com/oneapi-src/oneDNN/blob/main/CONTRIBUTING.md#code-contribution-guidelines).