This project was part of a university assignment concerning hardware architectures. It implements a variable-size shift/add multiplier architecture in HDL
The authors of this project are (in alphabetical order):
- George Evangelou (Dipl. Eng. Electrical and Computer Engineering Department, Univ. of Patras, Greece)
- Email: george_evangelou [at] windowslive.com
- LinkedIn profile
- Nick Roussos (Dipl. Eng. Electrical and Computer Engineering Department, Univ. of Patras, Greece)
- Email: nroussos97 [at] gmail.com
- LinkedIn profile
This repository is work in progress. Please contact the authors for any issue.