Mini16-ManyCore

FPGA many-core processor implementation written in Verilog HDL

Up to 501-core processors are implemented in a single FPGA

Features:

33 cores implemented, Fmax: 140 MHz / Terasic DE0-CV

171 cores implemented, Fmax: 100 MHz / BeMicro-CVA9

145 cores implemented, Fmax: 200 MHz / Kria KV260

with UART, VGA interface

65 cores implemented, Fmax: 140 MHz / Terasic DE0-CV

501 cores implemented, Fmax: 100 MHz / BeMicro-CVA9

An example of parallel processing of the Mandelbrot set

Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
asm		asm
bemicro_cva9		bemicro_cva9
bemicro_cva9_pe16		bemicro_cva9_pe16
de0-cv		de0-cv
de0-cv_pe16		de0-cv_pe16
kintex_usp		kintex_usp
kv260		kv260
testbench		testbench
tools		tools
cdc_synchronizer.v		cdc_synchronizer.v
dual_clk_ram.v		dual_clk_ram.v
fifo.v		fifo.v
harvester.v		harvester.v
mini16_cpu.v		mini16_cpu.v
mini16_pe.v		mini16_pe.v
mini16_soc.v		mini16_soc.v
r2w1_port_ram.v		r2w1_port_ram.v
readme.md		readme.md
rw_port_ram.v		rw_port_ram.v
shift_register.v		shift_register.v
sprite.v		sprite.v
uart.v		uart.v
uart_io.v		uart_io.v
vga_iface.v		vga_iface.v