Naïve MIPS32-like CPU design on a Xilinx FPGA
-
Five-stage pipeline
-
Data forwarding
-
One-instruction delay slot
-
No branch prediction
-
No privileged instructions
-
No interruptions or exceptions
Academic reference purpose only, contains bugs, not suitable for production.
sll
- Logical left shiftsrl
- Logical right shiftsra
- Arithmetical right shiftsllv
- Logical left shift by valuesrlv
- Logical right shift by valuesrav
- Arithmetical right shift by valuejr
- Jump by registerjalr
- Jump and link by registeradd
- Addaddu
- Add without overflow checksub
- Subtractsubu
- Subtract without overflow checkand
- Bitwise andor
- Bitwise orxor
- Bitwise exclusive ornor
- Bitwise not orslt
- Set if less thansltu
- Set if unsigned less than
beq
- Branch if equalbne
- Branch if not equaladdi
- Add immediate valueaddiu
- Add immediate value without overflow checkslti
- Set if less than immediate valuesltiu
- Set if less than unsigned immediate valueandi
- Bitwise and immediate valueori
- Bitwise or immediate valuexori
- Bitwise exclusive or immediate valuelui
- Load immediate value as upper half-wordlw
- Load word from memorysw
- Store word from memory
j
- Jumpjal
- Jump and link
la
- Load addressli
- Load immediate valuemove
- Move registernegu
- Negationnop
- No operationnot
- Bitwise notb
- Branchbal
- Branch and linkbeqz
- Branch if equal to zerobnez
- Branch if not equal to zero
Development board: Digilent Nexys 3
FPGA chip: Xilinx Spartan-6 xc6slx16-3csg324
-
clk (btn)
andrst
are controlled by two buttons, so you can single-step over the program. -
gclk
is driven by 100 MHz quartz crystal resonator. -
led_sel
is bond to 8 switches. -
led
powers the 4-digit seven-segmented display, showing values of different registers according toled_sel
.
Released under GNU General Public License version 3 (GPLv3).
See LICENSE for more information.