NB-LDPC code adapted to RISC-V Vector processor

Related article

Y. -M. Kuo, M. F. Flanagan, F. Garcia-Herrero, O. Ruano and J. A. Maestro, "Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension," in IEEE Transactions on Aerospace and Electronic Systems, doi: 10.1109/TAES.2023.3266314.

Authors

• Yao-Ming Kuo ykuo@ieee.org
• Mark F. Flanagan mark.flanagan@ieee.org
• Francisco Garcia-Herrero francg18@ucm.es
• Oscar Ruano oruano@ucm.es
• Juan Antonio Maestro jamaestro@ucm.es

Citations

In papers and reports, please refer to this work as follows:

@ARTICLE{10098873,

  author={Kuo, Yao-Ming and Flanagan, Mark F. and Garcia-Herrero, Francisco and Ruano, Õscar and Maestro, Juan Antonio},

  journal={IEEE Transactions on Aerospace and Electronic Systems}, 

  title={Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension}, 

  year={2023},

  volume={},

  number={},

  pages={1-12},

  doi={10.1109/TAES.2023.3266314}}