avr-delays

Include files for the AVRASM2 macro assembler, to generate code for precise delays.

1. DLC

The dlc.inc include file follows the same approach as the "AVR Delay Loop Calculator" web page, but is implemented using macros.

Example 1.1

.include "dlc.inc"              ; include delay macros

.equ F_CPU = 8000000            ; use default 8 MHz clock
.equ DLC_FIRST_HI_REG = 18      ; define the first register to use
.equ DLC_LAST_HI_REG = 20       ; define the last register that can be used

dlc_delay_ms 1000               ; generate delay for 1 second

This sets up DLC to generate code -by expanding macros- for an AVR that is clocked at 8 MHz, and the DLC is allowed to use the high registers R18 to R20. With this you can control the range of registers that DLC may use, so you can ensure no other registers gets overwritten accidentally by the expanded macro.

This example is useful for the scenario, when you have a fixed range of registers that can be used for this purpose, throughout your application.

You can use the dlc_delay_ms macro with a numeric argument to generate code that wastes clock cycles in the milliseconds range, and you can use the dlc_delay_us for the microseconds range.

Example 1.2

.include "dlc.inc"              ; include delay macros

.equ F_CPU = 8000000            ; use default 8 MHz clock

.set DLC_FIRST_HI_REG = 18      ; set the first register to use
.set DLC_LAST_HI_REG = 20       ; set the last register that can be used
dlc_delay_ms 1000               ; generate delay for 1 second (using this register range)

; some other code...

.set DLC_FIRST_HI_REG = 16      ; set the first register to use
.set DLC_LAST_HI_REG = 18       ; set the last register that can be used
dlc_delay_ms 1000               ; generate delay for 1 second (using other register range)

This example is useful for the scenario, when you want to use different register-ranges at different locations in your application for the macro expansion.

2. Delays

The delays.inc include file is based on Jan Huygh's implementation, but uses the same, configurable register range scheme as DLC, and an anologue API.

Example 2.1

.include "delays.inc"           ; include delay macros

.equ F_CPU = 8000000            ; use default 8 MHz clock
.equ DELAYS_FIRST_HI_REG = 18   ; define the first register to use
.equ DELAYS_LAST_HI_REG = 20    ; define the last register that can be used

delays_delay_ms 1000            ; generate delay for 1 second

Example 2.2

.include "delays.inc"           ; include delay macros

.equ F_CPU = 8000000            ; use default 8 MHz clock

.set DELAYS_FIRST_HI_REG = 18   ; set the first register to use
.set DELAYS_LAST_HI_REG = 20    ; set the last register that can be used
delays_delay_ms 1000            ; generate delay for 1 second (using this register range)

; some other code...

.set DELAYS_FIRST_HI_REG = 16   ; set the first register to use
.set DELAYS_LAST_HI_REG = 18    ; set the last register that can be used
delays_delay_ms 1000            ; generate delay for 1 second (using other register range)