This repository contains the VHDL source code to set up an FPGA design project for accelerating the step of creating contingency tables in the epistasis screening software HybridGWAIS. The sources are optimized for a Xilinx Kintex UltraScale KU115 FPGA attached to an Alpha Data ADM-PCIE-8K5 accelerator card.
Note: Due to licensing reasons, the top-level entity, that connects the main instance to the PCIe interface (for communication with the host) and to the two attached DRAM modules, is omitted. Also, whenever Xilinx IPs, such as BRAM or FIFO instances, are required, we instantiated a simple wrapper here, whose sources are not placed here for the same licensing reason.