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Merge pull request #19124 from hrydgard/minor-ir-optimization
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Minor IR interpreter optimizations
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hrydgard committed May 10, 2024
2 parents 9bef910 + 092179c commit e0e9620
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Showing 4 changed files with 17 additions and 25 deletions.
33 changes: 11 additions & 22 deletions Core/MIPS/IR/IRInterpreter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -283,33 +283,20 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
case IROp::LoadVec4:
{
u32 base = mips->r[inst->src1] + inst->constant;
#if defined(_M_SSE)
_mm_store_ps(&mips->f[inst->dest], _mm_load_ps((const float *)Memory::GetPointerUnchecked(base)));
#else
for (int i = 0; i < 4; i++)
mips->f[inst->dest + i] = Memory::ReadUnchecked_Float(base + 4 * i);
#endif
// This compiles to a nice SSE load/store on x86, and hopefully similar on ARM.
memcpy(&mips->f[inst->dest], Memory::GetPointerUnchecked(base), 4 * 4);
break;
}
case IROp::StoreVec4:
{
u32 base = mips->r[inst->src1] + inst->constant;
#if defined(_M_SSE)
_mm_store_ps((float *)Memory::GetPointerUnchecked(base), _mm_load_ps(&mips->f[inst->dest]));
#else
for (int i = 0; i < 4; i++)
Memory::WriteUnchecked_Float(mips->f[inst->dest + i], base + 4 * i);
#endif
memcpy((float *)Memory::GetPointerUnchecked(base), &mips->f[inst->dest], 4 * 4);
break;
}

case IROp::Vec4Init:
{
#if defined(_M_SSE)
_mm_store_ps(&mips->f[inst->dest], _mm_load_ps(vec4InitValues[inst->src1]));
#else
memcpy(&mips->f[inst->dest], vec4InitValues[inst->src1], 4 * sizeof(float));
#endif
break;
}

Expand Down Expand Up @@ -398,8 +385,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
#if defined(_M_SSE)
_mm_store_ps(&mips->f[inst->dest], _mm_mul_ps(_mm_load_ps(&mips->f[inst->src1]), _mm_set1_ps(mips->f[inst->src2])));
#else
const float factor = mips->f[inst->src2];
for (int i = 0; i < 4; i++)
mips->f[inst->dest + i] = mips->f[inst->src1 + i] * mips->f[inst->src2];
mips->f[inst->dest + i] = mips->f[inst->src1 + i] * factor;
#endif
break;
}
Expand Down Expand Up @@ -792,7 +780,7 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
mips->f[inst->dest] = mips->f[inst->src1] - mips->f[inst->src2];
break;
case IROp::FMul:
if ((my_isinf(mips->f[inst->src1]) && mips->f[inst->src2] == 0.0f) || (my_isinf(mips->f[inst->src2]) && mips->f[inst->src1] == 0.0f)) {
if ((mips->f[inst->src2] == 0.0f && my_isinf(mips->f[inst->src1])) || (mips->f[inst->src1] == 0.0f && my_isinf(mips->f[inst->src2]))) {
mips->fi[inst->dest] = 0x7fc00000;
} else {
mips->f[inst->dest] = mips->f[inst->src1] * mips->f[inst->src2];
Expand Down Expand Up @@ -1138,13 +1126,14 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
// Unimplemented IR op. Bad.
Crash();
}
#ifdef _DEBUG
if (mips->r[0] != 0)
Crash();
#endif
inst++;
}

#ifdef _DEBUG
if (mips->r[0] != 0)
Crash();
#endif

// We hit count. If this is a full block, it was badly constructed.
return 0;
}
3 changes: 1 addition & 2 deletions Core/MIPS/IR/IRJit.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -250,8 +250,7 @@ void IRJit::RunLoopUntil(u64 globalticks) {
u32 inst = Memory::ReadUnchecked_U32(mips_->pc);
u32 opcode = inst & 0xFF000000;
if (opcode == MIPS_EMUHACK_OPCODE) {
u32 data = inst & 0xFFFFFF;
IRBlock *block = blocks_.GetBlock(data);
IRBlock *block = blocks_.GetBlockUnchecked(inst & 0xFFFFFF);
u32 startPC = mips_->pc;
mips_->pc = IRInterpret(mips_, block->GetInstructions(), block->GetNumInstructions());
// Note: this will "jump to zero" on a badly constructed block missing exits.
Expand Down
3 changes: 3 additions & 0 deletions Core/MIPS/IR/IRJit.h
Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,9 @@ class IRBlockCache : public JitBlockCacheDebugInterface {
return nullptr;
}
}
IRBlock *GetBlockUnchecked(int i) {
return &blocks_[i];
}
const IRBlock *GetBlock(int i) const {
if (i >= 0 && i < (int)blocks_.size()) {
return &blocks_[i];
Expand Down
3 changes: 2 additions & 1 deletion Core/MIPS/MIPSIntVFPU.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -621,8 +621,9 @@ namespace MIPSInt
break;
default:
ApplySwizzleS(s, sz);
break;
}
for (int i = 0; i < n; i++) {
for (int i = 0; i < (int)n; i++) {
switch (optype) {
case 0: d[i] = s[i]; break; //vmov
case 1: d[i] = s[i]; break; //vabs (prefix)
Expand Down

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