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Add renesas ra8 support. #2601

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Add renesas ra8 support. #2601

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1 change: 1 addition & 0 deletions src/common/tusb_mcu.h
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Expand Up @@ -356,6 +356,7 @@
#elif TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N, OPT_MCU_RAXXX)
#define TUP_USBIP_RUSB2
#define TUP_DCD_ENDPOINT_MAX 10
#define TUP_RHPORT_HIGHSPEED 1
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You need to put this statement inside conditional check as other MCUs don't support HS. For example #if defined(BSP_MCU_GROUP_RA8M1)

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OK


//--------------------------------------------------------------------+
// GigaDevice
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33 changes: 31 additions & 2 deletions src/portable/renesas/rusb2/dcd_rusb2.c
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Expand Up @@ -173,6 +173,11 @@ static void pipe_write_packet(rusb2_reg_t * rusb, void *buf, volatile void *fifo

volatile uint16_t *ff16;
volatile uint8_t *ff8;

// flush cache
#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr(&_dcd, sizeof(dcd_data_t));
#endif

// Highspeed FIFO is 32-bit
if ( rusb2_is_highspeed_reg(rusb) ) {
Expand Down Expand Up @@ -221,6 +226,9 @@ static void pipe_write_packet_ff(rusb2_reg_t * rusb, tu_fifo_t *f, volatile void
uint16_t rem = total_len - count;
if (rem) {
rem = tu_min16(rem, info.len_wrap);
#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) info.ptr_wrap, 4), total_len - info.len_wrap + 31);
#endif
pipe_write_packet(rusb, info.ptr_wrap, fifo, rem);
count += rem;
}
Expand Down Expand Up @@ -508,6 +516,11 @@ static bool process_pipe_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_add
static bool process_edpt_xfer(rusb2_reg_t* rusb, int buffer_type, uint8_t ep_addr, void* buffer, uint16_t total_bytes)
{
const unsigned epn = tu_edpt_number(ep_addr);

#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) tu_align((uint32_t) buffer, 4), total_bytes + 31);
#endif

if (0 == epn) {
return process_pipe0_xfer(rusb, buffer_type, ep_addr, buffer, total_bytes);
} else {
Expand Down Expand Up @@ -661,6 +674,8 @@ static void enable_interrupt(uint32_t pswi)

void dcd_init(uint8_t rhport)
{
tu_memclr(&_dcd, sizeof(dcd_data_t));

rusb2_reg_t* rusb = RUSB2_REG(rhport);
rusb2_module_start(rhport, true);

Expand All @@ -669,10 +684,18 @@ void dcd_init(uint8_t rhport)
rusb->SYSCFG_b.HSE = 1;

// leave CLKSEL as default (0x11) 24Mhz

#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd, sizeof(dcd_data_t));
#endif
// Power and reset UTMI Phy
uint16_t physet = (rusb->PHYSET | RUSB2_PHYSET_PLLRESET_Msk) & ~RUSB2_PHYSET_DIRPD_Msk;
rusb->PHYSET = physet;

#if defined(RENESAS_CORTEX_M85)
// RA8 PHYSET-CLKSEL need set 20Mhz
rusb->PHYSET = (rusb->PHYSET & ~(1 << 4)) | (1 << 5);
#endif

R_BSP_SoftwareDelay((uint32_t) 1, BSP_DELAY_UNITS_MILLISECONDS);
rusb->PHYSET_b.PLLRESET = 0;

Expand Down Expand Up @@ -822,6 +845,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
*ctr = RUSB2_PIPE_CTR_PID_BUF;
}

#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd, sizeof(dcd_data_t));
#endif
// TU_LOG1("O %d %x %x\r\n", rusb->PIPESEL, rusb->PIPECFG, rusb->PIPEMAXP);
dcd_int_enable(rhport);

Expand Down Expand Up @@ -993,6 +1019,9 @@ void dcd_int_handler(uint8_t rhport)

// Control transfer stage changes
if ( is0 & RUSB2_INTSTS0_CTRT_Msk ) {
#ifdef __DCACHE_PRESENT
SCB_CleanInvalidateDCache_by_Addr((uint32_t*) &_dcd, sizeof(dcd_data_t));
#endif
if ( is0 & RUSB2_INTSTS0_CTSQ_CTRL_RDATA ) {
/* A setup packet has been received. */
process_setup_packet(rhport);
Expand Down Expand Up @@ -1025,4 +1054,4 @@ void dcd_int_handler(uint8_t rhport)
}
}

#endif
#endif
1 change: 1 addition & 0 deletions src/portable/renesas/rusb2/rusb2_type.h
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Expand Up @@ -48,6 +48,7 @@ extern "C" {
/* Start of definition of packed structs (used by the CCRX toolchain) */
TU_ATTR_PACKED_BEGIN
TU_ATTR_BIT_FIELD_ORDER_BEGIN
#pragma pack(2)
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I found that using the armclang compiler(ac6) without adding this code will cause it to not run properly.

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If pack is wrong it should be fixed in src/common/tusb_compiler.h


// TODO same as RUSB2_PIPE_TR_t
typedef struct TU_ATTR_PACKED _ccrx_evenaccess {
Expand Down