DWC2 DMA support #2576
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DWC2 DMA support #2576
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HiFiPhile
commented
Apr 6, 2024
HiFiPhile
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HiFiPhile
commented
Apr 25, 2024
| @@ -67,18 +67,6 @@ | |||
| // Debug level for DWC2 | |||
| #define DWC2_DEBUG 2 | |||
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| #ifndef dcache_clean | |||
| #define dcache_clean(_addr, _size) | |||
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dcache code should be removed and add MPU suggestion to make usb ram non cacheable:
- Not all internal buffers are aligned to cache line size and has size of multiple cache line size, speculative read or cache eviction of adjacent variables could lead to racing with DMA.
- Frequent cache clean invalidate hurt performance
- In most cases Cortex-M7 recommend use DTCM where cache is not used
HiFiPhile
commented
Apr 25, 2024
| static inline bool dma_enabled(uint8_t rhport) | ||
| { | ||
| // DMA doesn't support fifo transfer | ||
| #ifdef TUD_AUDIO_PREFER_RING_BUFFER |
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Don't want to depend on class driver but maybe it's the simplest way.
HiFiPhile
commented
Apr 25, 2024
| @@ -351,6 +382,12 @@ static void bus_reset(uint8_t rhport) { | |||
| // Setup the control endpoint 0 | |||
| _allocated_fifo_words_tx = 16; | |||
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| // DMA needs extra space for processing | |||
| if(dma_enabled(rhport)) { | |||
| uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; | |||
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Kernel use dwc2->ghwcfg3_bm.total_fifo_size it should be reliable.
We can even remove _dwc2_controller[rhport].ep_fifo_size and use this field instead, except GD32VF103 looks strange.
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|
Just tested the fix in 02ec486 and it solved the issue on my end as well 👍 |
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Describe the PR
Add Internal DMA support to DWC2.
Status
cdc_ual_portsaudio_4_channel_micvideo_capture_2chcdc_msc_freertosaudio_4_channel_mic_freertoshid_composite_freertosBenchmark
STM32F723E-DISCO
IAR 9.50 High-Balanced
I-Cache enabled
Method used in #920, all buffers set to 2048b.