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Google | OpenTitan Team
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hackdac_2018_beta
hackdac_2018_beta PublicForked from hackdac/hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
SystemVerilog 6
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cv32e40p
cv32e40p PublicForked from openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog
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opentitan
opentitan PublicForked from lowRISC/opentitan
OpenTitan: Open source silicon root of trust
SystemVerilog
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