Digital-Systems-and-Design

Learned as a component of the CS210 course.

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
Project		Project
ADDER_SUBTRACTOR.vhdl		ADDER_SUBTRACTOR.vhdl
AND2.VHDL		AND2.VHDL
BCD2SSD.vhdl		BCD2SSD.vhdl
BCD_ADD_SUB.vhdl		BCD_ADD_SUB.vhdl
BCD_COUNTER2.vhdl		BCD_COUNTER2.vhdl
BCD_TO_XS3.vhdl		BCD_TO_XS3.vhdl
CLK_DVD_1.vhdl		CLK_DVD_1.vhdl
CODE_CONVERTER.vhdl		CODE_CONVERTER.vhdl
COUNTER_ASYNC.vhdl		COUNTER_ASYNC.vhdl
COUNTER_SYNCR.vhdl		COUNTER_SYNCR.vhdl
CS210.VHDL		CS210.VHDL
DEMUX_1x2.vhdl		DEMUX_1x2.vhdl
DEMUX_1x4.vhdl		DEMUX_1x4.vhdl
D_FF.vhdl		D_FF.vhdl
D_FFN.vhdl		D_FFN.vhdl
D_LATCH.vhdl		D_LATCH.vhdl
D_LATCHN.vhdl		D_LATCHN.vhdl
FOUR_BIT_ADDER.vhdl		FOUR_BIT_ADDER.vhdl
FULL_ADDER.vhdl		FULL_ADDER.vhdl
HALF_ADDER.vhdl		HALF_ADDER.vhdl
MODULO_10_COUNTER.vhdl		MODULO_10_COUNTER.vhdl
MULTIPLIER.vhdl		MULTIPLIER.vhdl
MUX_2x1.vhdl		MUX_2x1.vhdl
MUX_4x1.vhdl		MUX_4x1.vhdl
NOT1.vhdl		NOT1.vhdl
OR2.vhdl		OR2.vhdl
README.md		README.md
SR_LATCH.vhdl		SR_LATCH.vhdl
SSD_UPDN.vhdl		SSD_UPDN.vhdl
XNOR1.vhdl		XNOR1.vhdl
XOR2.vhdl		XOR2.vhdl

gautamop01/Digital-Systems-and-Design