Skip to content
View flasonil's full-sized avatar
😄
Happy New Year!!
😄
Happy New Year!!

Highlights

  • Pro
Block or Report

Block or report flasonil

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. Deep-Neural-Network-for-CS-based-signal-reconstruction-on-STM32-MCU-board Deep-Neural-Network-for-CS-based-signal-reconstruction-on-STM32-MCU-board Public

    Compressed Sensing signal decoding with DNN oracle on STM32

    Python 14 1

  2. Serial-Multiplier Serial-Multiplier Public

    16 bit serial multiplier in SystemVerilog

    SystemVerilog 12 5

  3. APB_PWM APB_PWM Public

    Pulse Width Modulator programmed through an Advanced Peripheral Bus interface

    SystemVerilog 7 1

  4. riscv riscv Public

    SystemVerilog 2

  5. ripple_carry_adder ripple_carry_adder Public

    SystemVerilog 1

  6. CMOS_2stage_op-amp_design CMOS_2stage_op-amp_design Public

    SourcePawn 1