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Add sve targets #2886
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Add sve targets #2886
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Please don't add a faiss/python/swigfaiss_sve.swig file. |
Oh, sorry. I missed but that has been copied at this line. I removed the file and added the path on |
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🤨 |
Ah, #2917, OK. |
@mdouze How about the current status of this PR? |
So the diff only changes the compilation flags, it does not add VSE specific SIMD implementations, right? |
In this PR faiss uses SVE only with auto vectorized functions like |
As I wrote before,
It will include SVE implmemtations of |
@mdouze IMO the PRs should be separated, but I'm willing to include the commits of performance improvement in this PR if you want it. How would you like it? |
Sorry for being a bit slow to react. |
@mdouze OK. When you will want my action like:
please feel free to send me some comments. Anyway, I will wait the checking for a while. Thanks. |
@mdouze and @vorj is there any update on adding SVE support and do you guys still have plans to add it? I saw some discussion on the other PR and there was no activity since a while. Basically, we were looking for some optimization to Scalar Quantization(specifically SQfp16) on ARM like AVX2 on x86. Also, please let us know if you need any help to run tests for SVE support. We have bandwidth and resources to run tests. Thanks! |
@naveentatikonda I am just a contributor not employed by Meta, so actually I don't know the plans on this (official faiss) repository. However, as I told above, I have further patches to improve performance more, and I will create PR when this merged. |
@mdouze Did you get a chance to look into my question? |
OK so I think a way to move forward is to accept this PR but not cover it with CI.
Is there a doc somewhere that shows what current and future ARM implementaitons support SVE ? Thanks |
Would you mind rebasing on the latest Faiss so that I can import it to the internal Faiss version? |
I can assist and review the code, if needed |
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At least, current and future CPUs implemented ARMv9 will support SVE, because SVE2 is in the basic instruction set of ARMv9. Cortex-A510, Cortex-X2, Neoverse N2, Neoverse V2 are supporting ARMv9. However, I don't know that concrete implementations (real CPUs) will has ARMv9 or SVE, as this is decided by manufacturers. |
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@vorj Do you also have plans to add sve support to ScalarQuantization after this PR is merged? |
Currently I don't have the SVE version of ScalarQuantization, so you will be able to contribute it. However, I will speed it up that the unoptimized codes I will find on some times to spare. If I will find no SVE ScalarQuantization codes at my faiss-optimizing time, I will do that. |
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I did it. Would you review this? |
Just want to add a note here that this change is also very important to Nvidia RAPIDS libraries, as we're gearing up to have more libraries optimized for the Grace architecture. |
related: #2884
This PR contains below changes:
sve
faiss_sve
andswigfaiss_sve
-DFAISS_OPT_LEVEL=sve
at build time_swigfaiss_avx2.so
and_swigfaiss.so
)-msve-vector-length=
option_swigfaiss.so
,_swigfaiss_sve.so
,_swigfaiss_sve128.so
,_swigfaiss_sve256.so
,_swigfaiss_sve512.so
,_swigfaiss_sve1024.so
, and_swigfaiss_sve2048.so
. The package size will be exploded.faiss_sve
detects the vector length at run time.swigfaiss_sve
dynamicallyNOTE: I plan to make one more PR about add some SVE implementation after this PR merged. This PR only contains adding sve target.