DSP Engineer Intern @ Goodix India | Ex-Associate Software Engineer @ ATC
π¨βπ: M.Tech | NIT Durgapur
π«: B.Tech (E.C.E) | NIT Silchar
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Implementation-of-a-32-bit-RISC-V-CPU-Core-using-Transaction--Level-Verilog
Implementation-of-a-32-bit-RISC-V-CPU-Core-using-Transaction--Level-Verilog PublicBuilding a 32-bit RISC-V CPU Core using TL-verilog
Verilog
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