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REM.asc
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Version 4
SHEET 1 9124 2520
WIRE -800 -1040 -800 -1056
WIRE 304 -1024 304 -1040
WIRE -800 -944 -800 -960
WIRE 304 -928 304 -944
WIRE -800 -880 -800 -896
WIRE -240 -864 -240 -880
WIRE -800 -784 -800 -800
WIRE -240 -768 -240 -784
WIRE -800 -624 -800 -656
WIRE -608 -624 -608 -656
WIRE -432 -624 -432 -656
WIRE -800 -512 -800 -544
WIRE -608 -512 -608 -544
WIRE -432 -512 -432 -544
WIRE 784 -224 768 -224
WIRE 784 -208 768 -208
WIRE 880 -208 864 -208
WIRE 1600 -208 1584 -208
WIRE 1584 -192 1584 -208
WIRE 880 -160 880 -208
WIRE 880 -144 880 -160
WIRE 1600 -144 1600 -208
WIRE 1600 -144 1584 -144
WIRE 1536 -112 1504 -112
WIRE 1728 -96 1728 -128
WIRE 1728 -96 1584 -96
WIRE 1584 -80 1584 -96
WIRE 880 -32 880 -48
WIRE 944 -32 880 -32
WIRE 1104 -32 1040 -32
WIRE 1136 -32 1104 -32
WIRE 1600 -32 1584 -32
WIRE 1136 -16 1136 -32
WIRE 1504 0 1504 -112
WIRE 1536 0 1504 0
WIRE 960 16 960 0
WIRE 992 16 992 0
WIRE 1024 16 1024 0
WIRE 1024 16 992 16
WIRE 1600 16 1600 -32
WIRE 1600 16 1584 16
WIRE 1152 80 1136 80
WIRE 1248 80 1232 80
WIRE 1504 80 1504 0
WIRE 1248 96 1248 80
WIRE 1504 128 1504 80
WIRE 880 176 880 -32
WIRE 896 176 880 176
WIRE 1104 176 1104 -32
WIRE 1104 176 1088 176
WIRE 1504 224 1504 208
WIRE 1056 352 992 352
WIRE 992 384 992 352
WIRE 1008 384 992 384
WIRE 992 416 992 384
WIRE 992 416 928 416
WIRE 880 448 880 432
WIRE 1104 448 1104 432
WIRE 1680 608 1568 608
WIRE 1840 608 1680 608
WIRE 1056 640 992 640
WIRE 992 672 992 640
WIRE 1008 672 992 672
WIRE 1520 688 1488 688
WIRE 1792 688 1760 688
WIRE 992 704 992 672
WIRE 992 704 928 704
WIRE 1632 704 1632 624
WIRE 1632 704 1568 704
WIRE 1888 704 1888 624
WIRE 1888 704 1840 704
WIRE 1488 736 1488 688
WIRE 1488 736 1472 736
WIRE 1760 736 1760 688
WIRE 1760 736 1744 736
WIRE 1488 784 1488 736
WIRE 1520 784 1488 784
WIRE 1568 784 1568 752
WIRE 1760 784 1760 736
WIRE 1792 784 1760 784
WIRE 1840 784 1840 752
FLAG -800 -784 0
FLAG -800 -896 Eq
FLAG -800 -512 0
FLAG -800 -656 VARY
FLAG -608 -512 0
FLAG -608 -656 HV
FLAG 768 -208 rr
FLAG 768 -224 pc1
FLAG 1248 96 0
FLAG 880 -160 bl_end
FLAG 880 -32 bl_init
FLAG 960 16 HV
FLAG 992 16 Eq
FLAG -240 -960 0
FLAG -240 -1040 sn
FLAG -240 -768 0
FLAG -240 -880 sp
FLAG -432 -512 0
FLAG -432 -656 VOD
FLAG 1024 160 VOD
FLAG 928 208 sn
FLAG 1104 -32 blb
FLAG 944 160 VARY
FLAG 976 208 sp
FLAG 1040 208 sp_od
FLAG 304 -928 0
FLAG 304 -1040 sp_od
FLAG 1504 224 0
FLAG 1728 -224 rr
FLAG 1600 16 0
FLAG 1680 -208 0
FLAG 1504 80 vrr
FLAG 1728 0 0
FLAG -800 -944 0
FLAG -800 -1056 Eq
FLAG 1008 384 CSL_logic
FLAG 1104 384 0
FLAG 880 384 0
FLAG 880 448 lio
FLAG 1104 448 liob
FLAG 880 720 out
FLAG 1104 720 outb
FLAG 1008 672 MIO_logic
FLAG 1104 672 0
FLAG 880 672 0
FLAG 1568 800 0
FLAG 1680 608 write_on_logic
FLAG 1472 736 data_logic_t
FLAG 1568 656 vperi
FLAG 1840 800 0
FLAG 1744 736 data_logic_b
FLAG 1840 656 vperi
DATAFLAG 304 -1056 ""
DATAFLAG 304 -1056 ""
DATAFLAG 304 -1056 ""
DATAFLAG 768 -224 ""
DATAFLAG 768 -224 ""
DATAFLAG 768 -224 ""
DATAFLAG 768 -224 ""
SYMBOL voltage -800 -896 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -72 39 Left 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V_EQ
SYMATTR Value PWL(0 {eq_voltage} {time_eq_1} {eq_voltage} {time_eq_1+trise} 0)
SYMATTR SpiceLine Rser=100 Cpar=1f
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {vary_voltage}
SYMATTR InstName VARY_source
SYMBOL voltage -608 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {vary_voltage/2}
SYMATTR InstName V_HALFVARY
SYMBOL transmission_line 1136 32 R270
SYMATTR InstName X4
SYMATTR SpiceLine R=R_per_cell C=C_per_cell
SYMBOL dram_cell 848 -192 R0
SYMATTR SpiceLine cell_init_voltage_X={if(value_cr==0,{vary_voltage/2-offs},{vary_voltage/2+offs})}
SYMATTR InstName cell_requested
SYMBOL dram_cell 1168 64 R180
WINDOW 0 -25 -40 Invisible 2
SYMATTR InstName cell3
SYMATTR SpiceLine cell_init_voltage_X={if(value_cr==0,{vary_voltage/2-offs},{vary_voltage/2+offs})}
SYMBOL transmission_line 880 -96 R270
SYMATTR InstName X8
SYMATTR SpiceLine R=R_per_cell C=C_per_cell
SYMBOL equalizer 976 16 R0
SYMATTR InstName Equalizer
SYMBOL bv -240 -1056 R0
SYMATTR InstName B1_sn
SYMATTR Value V=((V(sp_od)+V(sp))*{vary_voltage}/{wordline_voltage})
SYMBOL voltage -240 -880 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -72 39 Left 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V_sp
SYMATTR Value PWL(0 0 {time_eq_1+nsense+trise+time_od} 0 {time_eq_1+nsense+trise+time_od+trise} {wordline_voltage} {time_eq_1+tras} {wordline_voltage} {time_eq_1+tras+trise} 0)
SYMATTR SpiceLine Rser=100 Cpar=1f
SYMBOL voltage -432 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {voltage_od}
SYMATTR InstName VARY_source1
SYMBOL sense_amplifier 960 224 R0
SYMATTR InstName X5
SYMATTR SpiceLine SA_nmos_L_=SA_nmos_L_w SA_nmos_W_=SA_nmos_W_w SA_pmos_L_=SA_pmos_L_w SA_pmos_W_=SA_pmos_W_w SA_nset_L_=SA_nset_L_w SA_nset_W_=SA_nset_W_w SA_pset_W_=SA_pset_W_w SA_pset_L_=SA_pset_L_w SA_pset_Lod_=SA_pset_Lod_w SA_pset_Wod_=SA_pset_Wod_w
SYMBOL voltage 304 -1040 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -72 39 Left 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V_sp1
SYMATTR Value PWL(0 0 {time_eq_1+nsense} 0 {time_eq_1+nsense+trise} {wordline_voltage} {time_eq_1+nsense+trise+time_od} {wordline_voltage} {time_eq_1+nsense+trise+trise+time_od} 0)
SYMATTR SpiceLine Rser=100 Cpar=1f
SYMBOL voltage 1504 112 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -72 39 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 57 Left 2
SYMATTR InstName V_Rr
SYMATTR Value PWL(0 {wordline_voltage} {time_eq_1} {wordline_voltage} {time_eq_1+trise} 0)
SYMATTR SpiceLine Rser=0 Cpar=0
SYMBOL transmission_line 1728 -176 R270
SYMATTR SpiceLine R=WL_R_per_cell C=WL_C_per_cell
SYMATTR InstName X3
SYMBOL transmission_line 1728 -48 R270
SYMATTR SpiceLine R=WL_R_per_cell C=WL_C_per_cell
SYMATTR InstName X10
SYMBOL nmos4 1536 -80 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M13
SYMATTR Value2 l={mc(0.1u,0.05)} w={mc(0.256u,0.05)}
SYMBOL pmos4 1536 -192 R0
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M14
SYMATTR Value2 l={mc(0.104u,0.05)} w={mc(0.908u,0.05)}
SYMBOL bv 1584 -208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName B2
SYMATTR Value V=-V(vrr)+{wordline_voltage}
SYMBOL voltage -800 -1056 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -72 39 Left 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V_EQ1
SYMATTR Value PWL(0 {eq_voltage} {time_eq_1} {eq_voltage} {time_eq_1+trise} 0)
SYMATTR SpiceLine Rser=100 Cpar=1f
SYMBOL nmos4 1056 432 M180
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc({SA_nmos_L_csl},mc_variation)} w={mc({SA_nmos_W_csl},mc_variation)}
SYMBOL nmos4 928 336 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc({SA_nmos_L_csl},mc_variation)} w={mc({SA_nmos_W_csl},mc_variation)}
SYMBOL transmission_line 880 496 R270
SYMATTR InstName X1
SYMATTR SpiceLine R=LIO_R_per_cell C=LIO_C_per_cell
SYMBOL transmission_line 1104 496 R270
SYMATTR InstName X2
SYMATTR SpiceLine R=R_per_cell C=LIO_C_per_cell
SYMBOL transmission_line 880 768 R270
SYMATTR InstName X6
SYMATTR SpiceLine R=MIO_R_per_cell C=MIO_C_per_cell
SYMBOL transmission_line 1104 768 R270
SYMATTR InstName X7
SYMATTR SpiceLine R=R_per_cell C=LIO_C_per_cell
SYMBOL nmos4 928 624 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc({SA_nmos_L_B},mc_variation)} w={mc({SA_nmos_W_B},mc_variation)}
SYMBOL nmos4 1056 720 M180
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc({SA_nmos_L_B},mc_variation)} w={mc({SA_nmos_W_B},mc_variation)}
SYMBOL nmos4 1520 704 R0
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_nmos_L_write, mc_variation)} w={mc(SA_nmos_W_write, mc_variation)}
SYMBOL pmos4 1520 608 R0
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_pmos_L_write, mc_variation)} w={mc(SA_pmos_W_write, mc_variation)}
SYMBOL nmos4 1792 704 R0
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M7
SYMATTR Value2 l={mc(SA_nmos_L_write, mc_variation)} w={mc(SA_nmos_W_write, mc_variation)}
SYMBOL pmos4 1792 608 R0
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M8
SYMATTR Value2 l={mc(SA_pmos_L_write, mc_variation)} w={mc(SA_pmos_W_write, mc_variation)}
TEXT 40 -560 Left 2 !.include ./22nm_HP.pm
TEXT 40 -584 Left 2 !.tran {sim_duration}
TEXT 40 -632 Left 2 !.param mc_variation=0.05
TEXT 48 376 Left 2 !.param capacitance={17f}
TEXT 48 400 Left 2 !.param C_per_cell={0.04f}
TEXT -560 -24 Left 2 !.param access_tran_L={208nm}
TEXT -560 0 Left 2 !.param access_tran_W={129n}
TEXT 48 312 Left 2 !.param R_per_cell=880*41.5/{cells_per_BL}
TEXT 48 280 Left 2 ;Bitline Resistance
TEXT -856 368 Left 2 !.param SA_eq_L=100n
TEXT -856 392 Left 2 !.param SA_eq_W=100n
TEXT 48 344 Left 2 !.param cells_per_BL=512
TEXT -872 -424 Left 2 !.param vary_voltage=1V
TEXT -872 -400 Left 2 !.param wordline_voltage=2.5V
TEXT -872 -328 Left 2 !.param common_plate={vary_voltage/2}
TEXT 40 -464 Left 2 !.param nsense=4ns
TEXT 48 496 Left 2 !.param WL_C_per_cell=0.078fF
TEXT 48 440 Left 2 ;Wordline Parasitics
TEXT 48 464 Left 2 !.param cells_per_LWL=1024
TEXT 48 528 Left 2 !.param WL_R_per_cell=760*85.5/{cells_per_LWL}
TEXT 40 -680 Left 2 !.TEMP 85
TEXT 40 -488 Left 2 !.param tras=32n
TEXT 40 -656 Left 2 !.param trise=0.5n
TEXT -560 -144 Left 2 !.param SA_nmos_L_w={SA_nmos_L_init}
TEXT -560 -120 Left 2 !.param SA_nmos_W_w={SA_nmos_W_init}
TEXT -560 -88 Left 2 !.param SA_pmos_L_w={SA_pmos_L_init}
TEXT -560 -64 Left 2 !.param SA_pmos_W_w={SA_pmos_W_init}
TEXT -560 40 Left 2 !.param SA_nset_L_w={SA_nset_L_init}
TEXT -560 64 Left 2 !.param SA_nset_W_w={SA_nset_W_init}
TEXT -560 104 Left 2 !.param SA_pset_Lod_w={SA_pset_L_init_od}
TEXT -560 128 Left 2 !.param SA_pset_Wod_w={SA_pset_W_init_od}
TEXT 40 -440 Left 2 !.param time_eq=5n time_eq_1={time_eq}
TEXT 40 -608 Left 2 !.param sim_duration={time_eq+{tras}+1n}
TEXT -664 368 Left 2 !.param SA_eq_L_half=100n
TEXT -664 392 Left 2 !.param SA_eq_W_half=188n
TEXT -864 88 Left 2 !.param SA_nmos_L_init={107nm}
TEXT -864 112 Left 2 !.param SA_nmos_W_init={530nm}
TEXT -864 144 Left 2 !.param SA_pmos_L_init={106nm}
TEXT -864 168 Left 2 !.param SA_pmos_W_init={380nm}
TEXT -864 200 Left 2 !.param SA_nset_L_init={90nm}
TEXT -864 224 Left 2 !.param SA_nset_W_init={149um/512}
TEXT -864 264 Left 2 !.param SA_pset_L_init_od={100nm}
TEXT -864 288 Left 2 !.param SA_pset_W_init_od={(54.808um+47.222um)/512}
TEXT -864 312 Left 2 !.param SA_pset_W_init={1.44*4um*2/512}
TEXT 40 -536 Left 2 !.ic V(bl_end)={vary_voltage/2} V(bl_init)={vary_voltage/2} V(blb)={vary_voltage/2}
TEXT -872 -376 Left 2 !.param eq_voltage=1.5V
TEXT 48 -144 Left 2 !.param LIO_C_per_cell={LIO_um*LIO_C_per_um/512}
TEXT 48 -208 Left 2 !.param LIO_C_per_um=0.306f
TEXT 48 -240 Left 2 ;LIO Resistance
TEXT 48 -176 Left 2 !.param LIO_um=85.5
TEXT 48 -112 Left 2 ;Here, CELL is intended of the transmission line to simulate C/R
TEXT 48 -88 Left 2 !.param LIO_block_area_ums={0.20*0.22*{LIO_um/0.20}}
TEXT 48 -56 Left 2 !.param LIO_R={LIO_block_area_ums*0.092}
TEXT 48 -24 Left 2 !.param LIO_R_per_cell={LIO_R/512}
TEXT 40 128 Left 2 !.param MIO_C_per_cell={MIO_um*LIO_C_per_um/512}
TEXT 40 64 Left 2 !.param MIO_C_per_um=0.217f
TEXT 40 32 Left 2 ;MIO Resistance
TEXT 40 96 Left 2 !.param MIO_um=1900
TEXT 48 152 Left 2 ;Here, CELL is intended of the transmission line to simulate C/R
TEXT 40 184 Left 2 !.param MIO_block_area_ums={0.40*0.88*{MIO_um/0.40}}
TEXT 40 216 Left 2 !.param MIO_R={MIO_block_area_ums*0.042}
TEXT 40 248 Left 2 !.param MIO_R_per_cell={MIO_R/512}
TEXT -872 -352 Left 2 !.param vperi=1.1v
TEXT -864 -24 Left 2 !.param SA_nmos_L_B={0.10um}
TEXT -864 0 Left 2 !.param SA_nmos_W_B={1.7um}
TEXT -864 32 Left 2 !.param SA_nmos_L_csl={0.09um}
TEXT -864 56 Left 2 !.param SA_nmos_W_csl={0.30um}
TEXT -864 -136 Left 2 !.param SA_nmos_L_write={0.06um}
TEXT -864 -112 Left 2 !.param SA_nmos_W_write={1.44um*5}
TEXT -864 -80 Left 2 !.param SA_pmos_L_write={0.06um}
TEXT -864 -56 Left 2 !.param SA_pmos_W_write={2.0um}
TEXT 40 -416 Left 2 !.param offs=0.220
TEXT -864 336 Left 2 !.param SA_pset_L_init={100nm}
TEXT -872 -304 Left 2 !.param voltage_od=1.4V
TEXT -560 192 Left 2 !.param SA_pset_L_w={SA_pset_L_init}
TEXT -560 216 Left 2 !.param SA_pset_W_w={SA_pset_W_init}
TEXT 40 -392 Left 2 !.param time_od=3n
TEXT 40 -512 Left 2 !.param value_cr=1
TEXT -872 -720 Left 2 ;Voltage sources
TEXT -872 -1112 Left 2 ;Control sources
TEXT 1504 -288 Left 2 ;SWD and SWL
TEXT 40 -720 Left 2 ;Simulation settings
TEXT -864 -176 Left 2 ;Transistors sizes
TEXT 888 -296 Left 2 ;Sensing circuit
TEXT 880 296 Left 2 ;Column select (runs along an entire mat)
TEXT 1144 504 VLeft 2 ;LIO
TEXT 1144 776 VLeft 2 ;MIO
TEXT 888 592 Left 2 ;Connection to the MIO (runs along all mats)
TEXT 1488 544 Left 2 ;Write transistors
TEXT 232 -560 Left 2 !.include ./22nm_LP.pm