Anton/experimental fpga #298
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ProGTX
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Sep 22, 2021
mehdi-goli
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Nov 19, 2021
mehdi-goli
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* Rudimentary hipSYCL build integration. * Don't always use CPU profile for GEMM and set samples C++17 standard for hipSYCL. * Allow overriding HIPSYCL_TARGETS by environment variable as well. And output the selected SYCL implementation. * Move setting HIPSYCL_TARGETS to SYCL.cmake and add docs. * Clarify comment about HIPSYCL_TARGETS
Co-authored-by: Kumudha <kumudha.narasimhan@codeplay.com> Co-authored-by: Mehdi Goli <mehdi.goli@codeplay.com>
CMake supports having export files which describe the library to users seeking it in either the build tree or an installed directory. This means users can now specify `-Dsycl_blas_DIR=$install_path` during configuration and CMake will be able to locate the library and headers.
Instead of adding an absolute path to the interface include dirs, we should use the PUBLIC link, since any SYCL-BLAS target will transitively depend on ComputeCpp or some other SYCL implementation as well (SYCL-BLAS uses SYCL constructs in its public headers). Without this change, packages created by installing the project will have absolute paths of the machine it was built on, making the package unrelocatable. With it, a requisite of the SYCL library is added to the targets. The SDK includes are still propagated for the export file, but removed for installs, as the headers are installed alongside the SYCL-BLAS headers so can be found in the same location.
Co-authored-by: Kumudha KN <kumudha.narasimhan@codeplay.com>
- Enable testing of Product Reduction and fix issues with it - Remove testing of Division Reduction since the Division operator is not commutative
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Added modifications to the tests and benchmarks in order to use the ComputeCPP runtime fpga fix in the queue constructor.
When compiling with the SYCL_BLAS_FPGA flag the queue is constructed in the .hpp file included in the benchmark or test .cpp file so it passes in trough the compute++ compiler and has access to the new dummy kernel from the queue constructor. (Required for the FPGA)