RISC-V CPU

An experimental RISC-V CPU designed in VHDL for the Digilent Arty A7.

Running Rust

Modify sample_prog

./rust.sh
cp out/out.coe riscv_cpu.srcs/sources_1/rom.coe
vivado -mode tcl -source regen_rom.tcl

To run assembly, first the assembly has to be assembled, linked, and converted into a Xilinx coefficients file format. This can be done by running:

./build.sh

The coefficient file will now be in out/out.coe.

Copy the file into the Xilinx project sources:

cp out/out.coe riscv_cpu.srcs/sources_1/rom.coe

Regenerate the Block ROM IP:

vivado -mode tcl -source regen_rom.tcl

When you run the simulation, it should run the expected assembly.

This project is heavily inspired by Bruno Levy's work on RISC-V processors: Bruno Levy

Name		Name	Last commit message	Last commit date
Latest commit History 34 Commits
riscv_cpu.srcs		riscv_cpu.srcs
sample_prog		sample_prog
test_files		test_files
.gitignore		.gitignore
LICENSE		LICENSE
README.md		README.md
build.sh		build.sh
fn.asm		fn.asm
linker.ld		linker.ld
mem.asm		mem.asm
regen_rom.tcl		regen_rom.tcl
riscv_cpu.xpr		riscv_cpu.xpr
run_sim.tcl		run_sim.tcl
rust.sh		rust.sh
source.tcl		source.tcl
tb_top_behav1.wcfg		tb_top_behav1.wcfg