mtkCPU is a simple, clear, hackable and very inefficient implementation of RiscV ISA in Amaranth HDL. There is one main file cpu.py, that is including specific units (i.a. decoder, adder etc.)
- implements basic ISA
rv32i Machinemode andUsermode- traps and interrupts
- bsp (board specific files) generation - based on RTL code it generates proper
.hand.ccfiles - CSR registers support
- Virtual Memory System - allows for memory translation in
Usermode - Debug Module - connect GDB to the CPU!
Debug Module (DM) is a part of a CPU that exposes things like CPU registers, or memory bus via JTAG interface, so that one can control the running CPU from the host PC.
The DM implementation is compatible with RISC-V Debug Specs 1.0, which means that you can use mainstream openOCD and GDB and it will Just Work™.
NOTE: There are more serious future plans going for DM implementation - we are going to move it to a separate repository and form as a plugin that can be used with any other CPU implementation. Read more about future plans here.
The design was tested on ice40 FPGA on the iCEBreaker board.
See Quick Start Page and find out how simple it is to deploy fully functional mtkCPU with one command!
We provide one-liner that generates a bitstream with Block RAM memory initialized with a specified .elf's content!
Watch the GDB Demo on YouTube!
So the Quick start is really quick to start with, but it "embeds" program embedded in bitstream and loaded during board programming. In order to change the program, full bitstream rebuild is required.
Due to the fact, that mtkcpu implements Debug Module, we may load the program using GDB+openOCD. Changing program that is running is possible during runtime, without bitstream reprogramming. Also, you have full GDB debugging capabilities, like breakpoints and single-stepping. See openOCD+GDB Quick Start guide for more details.
mtkCPU is under active and keen development, and you are invited to become part of it! Just make sure first to read the contribution page.
- pure-assembly unit tests (more than 80 tests present, each instruction covered)
- single-block testbenches
- co-simulation with
openOCDandGDBtesting Debug Module - randomized tests (arithmetic and MMU) using riscv-dv framework from Google
pip3 install .
pytest -x -n4 mtkcpu/tests/For more information about how tests work, please refer to that file.
Amaranth HDL is a Python framework for digital design, it can compile either to netlist understandable by yosys or Verilog code (that you can place and route using vendor tools, e.g. Vivado)
- Language guide
- Robert Baruch's introduction
- LambdaConcept's Step by Step
- Robert Baruch's refreshed RiscV playlist
Some parts of mtkCPU were inspired by minerva CPU parts (LambdaConcept's property).