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19 Open 16 Closed
19 Open 16 Closed
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Issues list

Consider using sphinx for nice documentation
#107 opened Sep 18, 2020 by mithro
Open source Xilinx simulation models
#106 opened Sep 18, 2020 by mithro
Potential glitch and failure possible in generic_fifo: combinational logic output passed to the other clock domain
#101 opened Apr 24, 2017 by pbazarnik
Publishing releases
#100 opened Feb 24, 2017 by ghost
system_bd.tcl Vivado version upgrade gotcha
#98 opened Nov 28, 2016 by olajep
2
parallella_accelerator.v missing
#95 opened Aug 17, 2016 by jimmysitu
mio: pushback might be broken
#90 opened Jun 3, 2016 by olajep
mio: need a sticky rx_not_empty bit
#89 opened Jun 3, 2016 by olajep
oh_fifo_async: GENERIC target probably doesn't synthesize correctly in Vivado
#88 opened Jun 1, 2016 by olajep
1
oh_fifo_sync doesn't synthesize properly in Vivado
#87 opened Jun 1, 2016 by olajep
spi: master doesn't transfer 2 MSB in data byte
#84 opened May 24, 2016 by olajep
1
GPIO: Support 32-bit access
#67 opened Apr 18, 2016 by olajep
master branch parallella bitstreams broken
#66 opened Apr 15, 2016 by olajep
Consecutive writes to rxmmu table results in system freeze
#50 opened Feb 16, 2016 by olajep
6
txmmu/rxmmu: Need valid bit in page table entries
#48 opened Feb 12, 2016 by olajep
fpga for 7010 device may need reworking
#45 opened Jan 30, 2016 by peteasa
4
ELINK_VERSION platform field question
#44 opened Jan 27, 2016 by olajep
1
mailbox: Writes dissapear
#37 opened Jan 19, 2016 by olajep
14
writes to fpga regs during reset can get lost
#19 opened Nov 11, 2015 by olajep
2
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