IDEA

UCSD (RTL2GDS)

• Project Site
• Static Timing Analysis
• Clock Tree Synthesis
• Global Placement
• Global Router
• Gate Sizing
• SystemVerilog2Verilog
• Detailed Placement

University of Minnesota / Intel (Automated Analog Layout)

• Align

University of Illinos (STA)

• OpenTimer
• Cpp-TaskFlow
• DtCraft

Yale (Aysnchronous Design and Parallel Databases)

• Asynchronous Circuit Compiler
• ACT Project Page
• Asynchronous Memory Compiler
• Galois Parallel Framework

Purdue (Parasitic Extraction)

• First Principle Solvers

University of Utah (Logic Synthesis)

• Logic Synthesis Oracle

JITX (Intent Driven Board Design)

• JITX

University of Michigan (Intent Driven Analog Design)

• Datasheet Parser

University of Texas (Analog Layout)

• Magical
• Magical Test Circuits

Princeton/University of Washington (Design Advisors)

• OpenPiton
• OpenCelerity
• UW BSG Pipecleaner Suite
• Princeton OpenPiton Design Benchmark
• System Verilog to Verilog

External Dependancies

• GDS Viewer
• Limbo
• ABC
• Yosys
• EPFL Logic Synthesis Libs
• VTR
• Logic Synthesis Benchmarks
• TAU18 Contest