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44 Open 22 Closed
44 Open 22 Closed
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Issues list

Q: DMA, desc_len VS tlast in axi_dma_wr
#78 opened May 9, 2024 by abarajithan11
1
about AXI DMA
#76 opened May 8, 2024 by zengzhengqi0524
1
About AXI_FULL_CDC
#74 opened Mar 30, 2024 by LZR1567
2
about axi_ram
#73 opened Mar 23, 2024 by nViol3t
2
About the solution for deadlocks
#70 opened Feb 21, 2024 by omeag
14
about tb
#69 opened Feb 18, 2024 by Unicorn619
1
About width missmatch
#68 opened Feb 14, 2024 by a60626316
2
Timing issues with axi_dma_wr
#67 opened Jan 24, 2024 by KireinaHoro
Axi DMA consistently returns DECERR
#66 opened Jan 23, 2024 by EnricoGiordano1992
6
Will unprocessed awvalid signals be stored in AXI Crossbar?
#65 opened Jan 23, 2024 by omeag
6
Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master
#64 opened Jan 3, 2024 by constant007
4
about axi_ram design specification
#63 opened Dec 8, 2023 by Maani02
Q: Do axi_dma_rd and axi_dma_wr support out of order transactions?
#60 opened Nov 1, 2023 by abarajithan11
2
about AXI_VFIFO
#59 opened Sep 24, 2023 by Monster-Kee
3
awready and wready set high in master without slave value
#57 opened May 18, 2023 by sazam0
axi_interconnect Synthesis
#55 opened May 10, 2023 by GGbang2
1
AXI Lite interconnect in N to 1 configuration
#54 opened May 2, 2023 by Twistix
2
AXI Reset Signal
#53 opened May 2, 2023 by mkokki
About priority_encoder
#52 opened Mar 30, 2023 by GGbang2
4
AXI interconnect
#51 opened Mar 8, 2023 by ilamparithy01
2
Documentation for axil_interconnect
#50 opened Mar 6, 2023 by catkira
3
AxiLiteMaster hangs with Verilator
#48 opened Mar 5, 2023 by catkira
14
axil_adapter_wr : Modelsim error "part select is reversed"
#46 opened Feb 23, 2023 by peioazk
6
tb simulation failed
#45 opened Feb 23, 2023 by nashsrg
2
AXIL crossbar doesn't support M_ADDR_WIDTH < 12
#44 opened Feb 13, 2023 by martin-tanguay
8
ProTip! Follow long discussions with comments:>50.