GitHub - akitty/verilog-mips-processor

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commits
.gitignore		.gitignore
adder.v		adder.v
alu.v		alu.v
async_memory.v		async_memory.v
control.v		control.v
data_memory.v		data_memory.v
inst_rom.v		inst_rom.v
leftshift2.v		leftshift2.v
mux.v		mux.v
mux4to1.v		mux4to1.v
processor.v		processor.v
program_counter.v		program_counter.v
reg_file.v		reg_file.v
serial_buf.v		serial_buf.v
sign_extend.v		sign_extend.v
testbench.v		testbench.v
zero_extender.v		zero_extender.v