Support for Synchronous Reads for Register File

[ghost]

Hi Claire,

Awesome job with this RISCV core! It is just what I was looking for, compact, simple and elegant design.
I am doing a port to XILINX Series 7 FPGA, which unfortunately do not support asynchronous reads from BRAMs. Have you considered adding support for synchronous reads from a register file implemented with BRAMs?

All the best
Hugo