Pull requests: Xilinx/finn
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Fix RoundAndClipThresholds Transformation
#1030
opened Apr 6, 2024 by
iksnagreb
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5 tasks done
Add high-level support for communication through ACCL
#931
opened Dec 2, 2023 by
cantbeblank24
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[Build] Add support for Vivado implementation strategy v++ option
#909
opened Oct 17, 2023 by
jmonks-amd
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Fixed input clock/reset port name inference during stitching
#347
opened Jun 14, 2021 by
quetric
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