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LPSS Private Space

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alexandred edited this page Oct 9, 2015 · 6 revisions

As well as having registers related to its own functionality, each LPSS device exposes a private register space which gives access to more lower-level aspects of the hardware. Each LPSS device has its private registry at a certain offset in its memory space. These are listed below:

  • LPT - 0x800 (TODO: what is LPT?)
  • I2C
    • Lynxpoint - 0x800
    • Baytrail - 0x800
  • UART
    • Lynxpoint - 0x800
    • Baytrail - 0x800
  • SDIO
    • Lynxpoint - 0x1000
  • SPI - 0x400
    • Baytrail - 0x400
    • Braswell - 0x400

The following is the list of general private space registers:

  • 0x00 - Clock Gate

    • This bit needs to be set to 1 on initialisation in order for the host controller to communicate with slave devices

  • 0x04 - Rests

  • 0x20 - Transaction Interrupt Mask

    • The LPSS UART device has an extra transaction complete interrupt. This register used to mask the interrupts to prevent an interrupt flood. Its value should be set to
#define LPSS_TX_INT_MASK		BIT(1)

More information can be found in this datasheet: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf

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