The Vivado project used to generate the custom IP and to define the addressing mode of the RTL design inside the AXI4 peripheral, to then be included within an HDL wrapper in order to generate the final bitstream.
A set of PDF files aimed at describing the whole work at various levels of detail: please refer to the official report in order to get started on the Hardware-Based CTF project.
The collection of files needed to correctly configure the environment on the embedded platform——after being cloned into the board itself, they allow to start up the application, making it available to the end-user(s).
The original Vivado project featuring all the building blocks of the top-level entity, displaying heavily commented code plus some additional resources for testing purposes.