FPGA Floating Point Division (Single Precision)

Simple project using the floating point division IP Core's division functionality from Xilinx

NEXYS 4 DDR (Artix-7)

Block Diagram for Programming Logic System. Project: https://github.com/SnrNotHere16/FPGADivisionFloatingPoint/tree/main/FloatingPointDivisionNexys4DDR/FPFPGA/Division 0/0 = 7FC0_0000 = NaN -2/0 = FF80_0000 = -inf 2/0 = 7F80_0000 = inf 0/-2 = 8000_0000 = -0
0/2 = 0000_0000 = 0

Name		Name	Last commit message	Last commit date
Latest commit History 149 Commits
FPDivZYBO		FPDivZYBO
FloatingPointDivisionNexys4DDR		FloatingPointDivisionNexys4DDR
Images		Images
NEXYS4BlockDiagram.PNG		NEXYS4BlockDiagram.PNG
README.md		README.md
pg060-floating-point.pdf		pg060-floating-point.pdf