Skip to content
View ShyamRazesh's full-sized avatar
🎯
Focusing
🎯
Focusing
Block or Report

Block or report ShyamRazesh

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING Public

    2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)

    1

  2. VSD_TCL_workshop VSD_TCL_workshop Public

  3. RISC-V-Physical-Design-Implementation RISC-V-Physical-Design-Implementation Public

    The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three-stage pipelined processor which executes 32-bit instructions in program order.

  4. Digital-Soc-Design Digital-Soc-Design Public

    Forked from SANGESH007/Digital-Soc-Design

    This Repository contains the complete Soc Design of Picorv32a

    Verilog