🎯
Focusing
VLSI Design Enthusiast
Block or Report
Block or report ShyamRazesh
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePopular repositories
-
DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING Public2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organized by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE /Sky130)
-
-
RISC-V-Physical-Design-Implementation
RISC-V-Physical-Design-Implementation PublicThe RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three-stage pipelined processor which executes 32-bit instructions in program order.
-
Digital-Soc-Design
Digital-Soc-Design PublicForked from SANGESH007/Digital-Soc-Design
This Repository contains the complete Soc Design of Picorv32a
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.