n-bit binary counter with asynchronous reset in SystemVerilog.
n-bit binary to gray code combinational converter circuit in SystemVerilog.
Demultiplexer of parameterized width and parameterized number of output ports.
n-bit full adder in SystemVerilog
n-bit full subtractor in SystemVerilog
n-bit gray code counter with asynchronous reset implemented using binary counter and binary to gray code combinational converter circuit in SystemVerilog.
Multiplexer of parameterized width and parameterized number of input ports.