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Releases: RISCV-on-Microsemi-FPGA/RISC-V-Creative-Board

Libero v12.3 designs - v1.0

27 Feb 16:27
@kevinscully100 kevinscully100
12.3-v1.0
41297a2
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Libero v12.3 designs - v1.0 Pre-release
Pre-release

Updated to support Libero 12.3

  • Libero design Tcl scripts are unchanged
  • Updated README.md files to support Libero 12.3
  • Updated the BaseDesign io_constraints file (Libero_Projects/import/constraints/BaseDesign) to add a missing constraint that caused errors when debugging the AXI port of the design
Assets 2

Libero v12.1 designs - v0.1

26 Oct 02:03
@kevinscully100 kevinscully100
12.1-v0.1
4f84a3e
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Libero v12.1 designs - v0.1 Pre-release
Pre-release

Initial conversion of designs to Libero Tcl flow

Assets 2