Merge pull request #22 from RISCV-on-Microsemi-FPGA/develop

Merge to master Libero v12.6 designs

FlashPro_Express_Projects/README.MD

@@ -1,6 +1,6 @@
 # PolarFire Evaluation Kit FPGA Programming Files
 
-This folder contains FlashPro Express v12.4 projects for the PolarFire Evaluation Kit Mi-V sample designs.
+This folder contains FlashPro Express v12.6 projects for the PolarFire Evaluation Kit Mi-V sample designs.
 
 ## FlashPro Express
 The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
@@ -21,11 +21,11 @@ The programming files contained under this folder were exported from the designs
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V processor
+* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
-* Target memory is RAM
-* User peripherals (GPIO, Timers, UART)
+* Target memory is SRAM (32kB)
+* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
 
 The peripherals in this design are located at the following addresses.
 
@@ -36,4 +36,4 @@ The peripherals in this design are located at the following addresses.
 | CoreTimer_0   | 0x7000_3000   |
 | CoreTimer_1   | 0x7000_4000   |
 | CoreGPIO_OUT  | 0x7000_5000   |
-| RAM| 0x8000_0000|
+| SRAM| 0x8000_0000|

Libero_Projects/PF_Eval_Kit_ES_MiV_RV32IMAF_BaseDesign.tcl

@@ -8,21 +8,21 @@ set design_flow_stage [string toupper [lindex $argv 1]]
 
 proc create_new_project_label { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
 	puts "Creating a new project for the 'PF_Eval_Kit_ES' board."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
 proc project_exists { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
 	puts "Error: A project exists for the 'PF_Eval_Kit_ES' with this configuration."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
 proc no_first_argument_entered { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "No 1st Argument has been entered."
 	puts "Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' " 
 	puts "Default 'CFG1' design has been selected."
@@ -31,35 +31,56 @@ proc no_first_argument_entered { }\
 
 proc invalid_first_argument { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Wrong 1st Argument has been entered."
     puts "Make sure you enter a valid first argument -'CFG1..CFGn'."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
 proc no_second_argument_entered { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "No 2nd Argument has been entered."
 	puts "Enter the 2nd Argument after the 1st to be taken further in the Design Flow." 
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
 proc invalid_second_argument { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Wrong 2nd Argument has been entered."
     puts "Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
 proc  base_design_built { }\
 {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
 	puts "BaseDesign built."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 }
 
+proc download_cores_all_cfgs  { }\
+{
+	download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.6.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.2.107} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.5.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.108} -location {www.microchip-ip.com/repositories/SgCore} 
+	download_core -vlnv {Actel:SgCore:PF_OSC:1.0.102} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.203} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+	download_core -vlnv {Actel:SgCore:PF_CCC:2.2.100} -location {www.microchip-ip.com/repositories/SgCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.4.102} -location {www.microchip-ip.com/repositories/DirectCore}
+}
+
 proc pre_configure_place_and_route { }\
 {
 	# Configuring Place_and_Route tool for a timing pass.
@@ -76,7 +97,8 @@ if {"$config" == "CFG1"} then {
 		project_exists
 	} else {
 		create_new_project_label
-		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300T_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
+		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
+		download_cores_all_cfgs
 		source ./import/components/IMAF_CFG1/import_component_and_constraints_pf_eval_kits_rv32imaf_cfg1.tcl
 		save_project
         base_design_built
@@ -89,7 +111,8 @@ if {"$config" == "CFG1"} then {
 	} else {
 		no_first_argument_entered
 		create_new_project_label
-		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300T_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
+		new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} -adv_options {TEMPR:EXT} -adv_options {VCCI_1.2_VOLTR:EXT} -adv_options {VCCI_1.5_VOLTR:EXT} -adv_options {VCCI_1.8_VOLTR:EXT} -adv_options {VCCI_2.5_VOLTR:EXT} -adv_options {VCCI_3.3_VOLTR:EXT} -adv_options {VOLTR:EXT}
+		download_cores_all_cfgs
 		source ./import/components/IMAF_CFG1/import_component_and_constraints_pf_eval_kits_rv32imaf_cfg1.tcl
 		save_project
         base_design_built
@@ -98,38 +121,38 @@ if {"$config" == "CFG1"} then {
 
 
 if {"$design_flow_stage" == "SYNTHESIZE"} then {
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Begin Synthesis..."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
 	pre_configure_place_and_route
     run_tool -name {SYNTHESIZE}
     save_project
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Synthesis Complete."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
 
 } elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then {
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Begin Place and Route..."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
 	pre_configure_place_and_route
 	run_verify_timing
 	save_project
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Place and Route Complete."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
 
 
 } elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then {
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Generating Bitstream..."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
@@ -140,15 +163,15 @@ if {"$design_flow_stage" == "SYNTHESIZE"} then {
     run_tool -name {GENERATEPROGRAMMINGFILE}
     save_project
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Bitstream Generated."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
 
 
 } elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then {
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Exporting Programming Files..."
 	puts "--------------------------------------------------------------------------------------------------------- \n"
 
@@ -165,7 +188,7 @@ if {"$design_flow_stage" == "SYNTHESIZE"} then {
 			-bitstream_file_components {}
 		save_project
 
-	puts "\n ---------------------------------------------------------------------------------------------------------"
+	puts "\n---------------------------------------------------------------------------------------------------------"
     puts "Programming Files Exported."
 	puts "--------------------------------------------------------------------------------------------------------- \n"