This repository contains the Mi-V RISC-V CPUs packages, supporting IPs and related documentation.
- Designed for low power ASIC microcontroller and FPGA soft-core implementations
- Supports the RISC-V standard RV32I ISA with optional M and C extensions
- Availability of Tightly Coupled Memory, with size defined by address range
- Direct Access Port (DAP) to TCM
- External, Timer and Soft Interrupts
- Up to six optional external interrupts
- Vectored and non-vectored interrupt support
- Optional on-chip debug unit with a JTAG interface
- AHBL, APB3, and AXI3/AXI4 optional external bus interfaces
See the Mi-V RISC-V Ecosystem webpages for more information
- Designed for low power ASIC microcontroller and FPGA soft-core implementations
- Integrated 8Kbytes instructions cache and 8 Kbytes data cache
- A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupt with a single priority level
- Supports the RISCV standard RV32IMA ISA
- On-Chip debug unit with a JTAG interface
- Two external AHB interfaces for IO and memory
See the Mi-V RISC-V Ecosystem webpages for more information
- Designed for low power ASIC microcontroller and FPGA soft-core implementations
- Integrated 8Kbytes instructions cache and 8 Kbytes data cache
- A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupt with a single priority level
- Supports the RISCV standard RV32IMA ISA
- On-Chip debug unit with a JTAG interface
- Two external AXI interfaces for IO and memory
See the Mi-V RISC-V Ecosystem webpages for more information
- Designed for low power ASIC microcontroller and FPGA soft-core implementations
- Integrated 8Kbytes instructions cache and 8 Kbytes data cache
- A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupt with a single priority level
- Supports the RISCV standard RV32IMAF ISA
- On-Chip debug unit with a JTAG interface
- Two external AHB interfaces for IO and memory
See the Mi-V RISC-V Ecosystem webpages for more information