-
Notifications
You must be signed in to change notification settings - Fork 611
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
difftest: Support generating difftest bundles for make verilog
target
#2988
difftest: Support generating difftest bundles for make verilog
target
#2988
Conversation
I would like to add some comments here for future references. This Since difftest may create some hardware logic when some features are enabled (such as the squash/batch for better simulation speed on Palladium), the user must ensure that they are not using any advanced configurations of difftest to avoid Chisel elaboration errors. |
[Generated by IPC robot]
master branch:
|
#2975 bumps difftest as well. Github does not resolve the conflicts correctly, though the submodule update is forward. Need to rebase to master |
Previously, difftest bundles can only be generated when building `sim-verilog` target. The difftest can not be used when simulating design that use the output of `make verilog` target. This patch enable generating of difftest bundles for `make verilog` target, it can further be used to enable difftest support in simulation. Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>
1c32340
to
af82fe8
Compare
fixed |
[Generated by IPC robot]
master branch:
|
Previously, difftest bundles can only be generated when building
sim-verilog
target. The difftest can not be used when simulating design that use the output ofmake verilog
target.This patch enable generating of difftest bundles for
make verilog
target, it can further be used to enable difftest support in simulation.