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difftest: Support generating difftest bundles for make verilog target #2988

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merged 1 commit into from
May 17, 2024

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forever043
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Previously, difftest bundles can only be generated when building sim-verilog target. The difftest can not be used when simulating design that use the output of make verilog target.

This patch enable generating of difftest bundles for make verilog target, it can further be used to enable difftest support in simulation.

@poemonsense
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I would like to add some comments here for future references. This finish call is outside the hardware scope, and its execution is expected not to create any hardware (such as Wire, Reg, IO, ...). The expected output is only generated C++/verilog files.

Since difftest may create some hardware logic when some features are enabled (such as the squash/batch for better simulation speed on Palladium), the user must ensure that they are not using any advanced configurations of difftest to avoid Chisel elaboration errors.

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[Generated by IPC robot]
commit: 1c32340

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
1c32340 1.863 0.450 2.103 1.182 2.472 2.597 2.328 0.956 1.398 1.413 3.120 2.655 2.453 2.951

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
5961467 1.855 0.450 2.103 1.177 2.478 2.594 2.333 0.957 1.398 1.421 3.117 2.655 2.454 2.952
4b40434
9eee369 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
006b878 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
7299828 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
0c70648 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
b628978 1.854 0.450 2.103 1.190 2.468 2.593 2.329 0.960 1.377 1.427 3.123 2.639 2.451 2.960
5e237ba 0.450 2.103 2.328 1.377 2.639
363530d 1.841 1.190 2.478 2.597 0.961 1.391 3.126 2.452 2.959
a72b131

@poemonsense
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#2975 bumps difftest as well. Github does not resolve the conflicts correctly, though the submodule update is forward. Need to rebase to master

Previously, difftest bundles can only be generated when building `sim-verilog`
target. The difftest can not be used when simulating design that use the output
of `make verilog` target.

This patch enable generating of difftest bundles for `make verilog` target,
it can further be used to enable difftest support in simulation.

Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>
@forever043
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forever043 commented May 16, 2024

#2975 bumps difftest as well. Github does not resolve the conflicts correctly, though the submodule update is forward. Need to rebase to master

fixed

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[Generated by IPC robot]
commit: af82fe8

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
af82fe8 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
e778bb8 0.957
c83747b 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
d7a3496 1.855 0.450 2.103 1.177 2.478 2.594 2.332 0.957 1.398 1.421 3.117 2.655 2.454 2.952
5961467 1.855 0.450 2.103 1.177 2.478 2.594 2.333 0.957 1.398 1.421 3.117 2.655 2.454 2.952
4b40434
9eee369 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
006b878 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
7299828 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
0c70648 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
b628978 1.854 0.450 2.103 1.190 2.468 2.593 2.329 0.960 1.377 1.427 3.123 2.639 2.451 2.960

@poemonsense poemonsense merged commit 2316cea into OpenXiangShan:master May 17, 2024
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4 participants