Taming Your VCTCXO
All Software Defined Radios require an oscillator of some kind to provide a stable clock to the RF transceiver and any microcontrollers or FPGAs on the radio, the bladeRF is no exception. There are many types of oscillators, each having their own benefits and drawbacks -- cost, accuracy, stability, phase noise, power requirements, among others.
At the factory, the DAC output voltage is adjusted while the VCTCXO output frequency is measured using a frequency counter. Over time, and with changes in ambient conditions (e.g. morning shade and afternoon sunlight), this factory-calibrated DAC value may stop producing a sufficiently accurate clock frequency, or the accuracy may drift throughout the day. Although the clock will remain accurate enough for most applications, some applications have very strict clock accuracy requirements and this drift may violate specifications. In these scenarios, it is especially important to keep the VCTCXO stable and accurate. This is typically accomplished by comparing the local oscillator to a more accurate reference oscillator.
WIP, essentially this blog post
The bladeRF2‑micro features an on-board analog PLL (ADF4002) that may be used to lock the on-board 38.4 MHz VCTCXO to an external reference of nearly any frequency up to 300 MHz. The reference input is ac-coupled and internally biased to support either 3.3 V CMOS or sinusoidal reference inputs. The default frequency is 10 MHz in libbladeRF because it is a commonly used reference frequency in test equipment.
Once locked to its reference, the PLL will send pulses to its charge pump output. The pulses are proportional to the difference in frequency and phase between the scaled versions of the reference input and VCTCXO output. The result is a mostly steady-state DC voltage that supplies the tune input of the VCTCXO to hold it at "exactly" 38.4 MHz, and phase-locked to the 10 MHz reference input. The reference input must remain active at all times while using this PLL.
Apply a reference clock to the REFIN (J95) U.FL connector located along the top right edge of the bladeRF2‑micro, then issue the following bladeRF-cli command:
bladeRF> set clock_ref enableThe command will return the locked status of the PLL. It may initially report unlocked, but subsequent status readings should report locked:
bladeRF> print clock_ref
Clock reference: REFIN to ADF4002 (locked)If using a non-default reference frequency, it may be changed only after enabling the PLL. The following command shows how to set the reference frequency to 20 MHz:
bladeRF> set refin_freq 20M
REFIN frequency: 20000000 HzWhile it is possible to design a radio with the most accurate oscillator in the world, the frequency options are limited (usually just 10 MHz), very few entities would be able to afford it, and quite simply it's just not needed in the vast majority of use cases. Instead, a cheaper (but still highly accurate) oscillator is selected and it is tamed by an external, more accurate oscillator dictated by the application requirements. Some examples include:
- Most test equipment has a 10 MHz reference output
- bladeRF2‑micro: In most situations, this can be directly connected to the analog PLL reference input. The reference waveform may be either a square wave or a sinusoid, do not exceed 3.3 Vpp.
- bladeRF Classic: The VCTCXO taming is performed digitally and has a 1.8 V CMOS input (3.3 V tolerant). The reference oscillator must be a square wave; a sinusoid will result in significant phase noise.
- GPS Disciplined Oscillator (GPSDO) (~$200+)
- Oven-controlled XO (OCXO) (~$500+)
- Atomic clock or chip-scale atomic clock (CSAC), typically cesium or rubidium (~$1000+)
- Ethernet (White Rabbit, IEEE 1588 PTP) (>>$1000 due to infrastructure)