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Nidhinchandran47/README.md

Hey! I'm Nidhin Chandran.

  • ๐Ÿ‘€ ย Iโ€™m interested in Front-end VLSI Design
  • ๐ŸŒฑ ย Iโ€™m always learning new technologies and methodologies to improve my skills and expand my knowledge.
  • ๐Ÿ’ž๏ธ ย Iโ€™m looking for moments of peace
  • โšก ย Fun Fact : "I'm always there, front and center, for every Liverpool game." #YNWA

๐Ÿ“ซ ย How to reach me?

๐Ÿ”— ย My Free-time Crafts (Build with )

Top Langs GitHub Streak

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  1. my_rtl_code my_rtl_code Public

    Repository for RTL building blocks #100daysofrtl VERILOG VHDL System Verilog

    Verilog 10 1