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AArch64: fix ld<n>r destination registers #6470

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As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the ld2r, ld3r and ld4r instructions for AARCH64. According to Sections C7.2.182, C7.2.185 and C7.2.188, the expected behaviour is to load multiple register values into a set of destination registers. While the current behaviour instead uses the same destination register many times, never accessing the other registers.

@Sleigh-InSPECtor Sleigh-InSPECtor changed the title AA64: fix ld<n>r destination registers AArch64: fix ld<n>r destination registers Apr 30, 2024
@GhidorahRex GhidorahRex self-assigned this Apr 30, 2024
@GhidorahRex GhidorahRex added Type: Bug Something isn't working Feature: Processor/AARCH64 Status: Triage Information is being gathered labels Apr 30, 2024
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Feature: Processor/AARCH64 Status: Triage Information is being gathered Type: Bug Something isn't working
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