This repository houses my works from the undergraduate hardware description language course, demonstrating proficiency in Verilog and utilization of industry-standard tools such as ModelSim and Xilinx ISE.
This assignment involved designing and testing a sequential logic circuit using Verilog HDL. The objective was to gain hands-on experience in digital circuit design, Verilog modeling, and functional verification using ModelSim.
The goal was to enhance skills in structural modeling and test bench automation. I designed a 4-bit binary comparator in Verilog, created a structured test bench with predefined cases, and analyzed the simulation results. This assignment explored advanced Verilog concepts and complex digital design validation.
I developed a vending machine controller using the Spartan-6 FPGA in Xilinx ISE. The assignment focused on synthesizable finite state machine (FSM) designs. I coded and simulated the FSM module in Verilog, validating the design on the FPGA.
The final assignment involved designing and implementing a 4-bit biquadratic filter algorithm on an FPGA. I optimized the design for speed and analyzed resource utilization and timing. Concepts covered included RTL code development, floating-point to fixed-point conversion, and FPGA optimizations.