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Releases: MIPT-ILab/mipt-mips

MIPT-V 2022

24 May 11:49
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Adoption of C++20 for cleaner code:

  • Implementation-independent signed number representation
  • Concepts
  • Concept-constrained auto

Bug fixes

Convergence with mainline RISC-V opcodes

Testing infrastructure upgrades

  • LLVM 14

External bugs reported

MIPT-V / MIPT-MIPS 2021 Release 2

11 Dec 18:21
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RISC-V bit manipulation instructions

Testing infrastructure upgrades

  • LLVM 12

Extracted Flowchart visualizer to a separate repository: https://github.com/MIPT-ILab/PipelineFlowchartVis

MIPT-V / MIPT-MIPS 2021

28 Apr 20:25
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Pipeline Visualization Tool by BSUIR students Alex Kulsha and Andrei Karpyza under Anton Lechanka supervising.

RISC-V bit manipulation instructions

Performance Simulation

Bug fixes

  • #1257 follow up: pipeline must be flushed only once per cycle.
  • RISC-V bfp instruction fixed according to 0.92 specification.

Testing infrastructure upgrades

Switched to Github Actions from Travis CI

External PRs

MIPT-V / MIPT-MIPS 2020

26 Apr 14:52
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99.99% test coverage!

Functional simulation

Performance simulation

RISC-V

  • Support of SLLID, SRLID, SRAID, and ADDID instructions by Pavel Kryukov

Testing infrastructure upgrades

External PRs

MIPT-V / MIPT-MIPS 2019 Release 3

09 Dec 23:15
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RISC-V bit manipulation instructions

Performance simulation

Tools

Testing infrastructure upgrades

  • ARM-hosted builds on Travis CI
  • Clang-Tidy 9

New Manuals

External PRs

MIPT-MIPS / MIPT-V 2019 Release 2

09 Sep 09:28
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99% test coverage!

RISC-V

System simulation updates by Pavel Kryukov

  • MIPS32/MARS exception handling
  • System calls support for performance simulation
  • Interactive cycle-accurate modeling with GDB

Cache modeling

Outputs

External PRs

MIPT-MIPS / MIPT-V 2019

07 May 21:03
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98% test coverage!

RISC-V

System simulation

Branch prediction

Cache improvements by Andrey Agrachev

  • Infrastructure for cache replacement policies
  • Pseudo-LRU replacement policy
  • Use of Google Dense Hash for simulation speed

Execution pipeline improvement by Egor Bova

  • Initial support for multi-wide writeback stage

MIPS

  • Generation of MIPS traps by Vsevolod Pukhov
  • Unit tests for MIPS instructions by Egor Bova. Bug fixes:
    • Treat dadd and daddu as MIPS III instructions
    • Fix of 64-bit multiplication on x86 targets and/or VS builds
    • Branch-and-link instructions should link even if not taken
    • Use only LSB of the variable shift RHS operand (#709)
  • Decoding of CP1 (floating point) instructions by Egor Bova.
  • Support of branch delay slot by Pavel Kryukov and Andrey Agrachev
  • Big-endian MIPS by Pavel Kryukov

Complete refactoring of port system by Pavel Kryukov

  • Dynamic type matching
  • Self-cleaning
  • Arena allocations with optimizations for POD-based data structures
  • Type erasure for ports to reduce amount of templates
  • Translation of port templates in a separate translation unit
  • As a result, 1.5x simulation speed and 2x compilation speed boosts

New manuals

External PRs:

MIPT-MIPS 2018 release 3

07 Feb 09:04
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MIPS

  • Compatibility with basic MARS system calls conventions by Vyacheslav Kompan
  • Interactive functional simulation mode with GDB by Vyacheslav Kompan
  • Interface-level integration to cycle-accurate simulation of Nintendo® 64 in CEN64 environment by Pavel Kryukov

Branch prediction

Quality assurance

  • Unit tests for MIPS instructions by Vsevolod Pukhov. One bug reported.
  • Unit test coverage for branch prediction modes by Yan Logovsky. One bug reported.

Code quality

New manuals:

External PRs:

MIPT-MIPS 2018 release 2

05 Oct 14:22
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Micro-architectural precision:

  • Support bypass for MIPS mthi instruction by Denis Los

Quality assurance:

Bug fixes:

  • MIPS64: fixes for LWL, SWL, and SRL instructions by Pavel Kryukov

Integration of portable libraries:

New manuals:

External PRs:

MIPT-MIPS 2018

10 May 09:44
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Micro-architectural precision:

Support of more MIPS instructions:

  • Multiplication and division instructions:
  • Accumulating multiplication of MIPS32 by Andrei Sultan: madd, maddu, msub, msubu
  • Unaligned memory accesses by Andrei Sultan: lwl, lwr, swl, swr
  • Linked loads/conditional stores without atomicity warranties by Pavel Kryukov: ll, sc

MIPS64 infrastructure and experimental implementation of instructions by Kirill Nedostoev, Alexander Timofeev, and Pavel Kryukov

  • Doubleword arithmetics (MIPS III): dadd, daddiu, daddu, dsub, dsubu
  • Doubleword shifts (MIPS III): dsll, dsll32, dsra, dsra32, dsrl, dsrl32
  • Doubleword variable shifts (MIPS III): dsllv, dsrav, dsrlv
  • Doubleword memory accesses (MIPS III): ld, lwu, sd, lld, scd
  • Doubleword multiplication/division (MIPS III): ddiv, ddivu, dmult, dmultu
  • Doubleword count leading zeroes/ones (MIPS64): dclo, dclz

RISC-V preparations by Aleksandr Misevich:

  • Generalized infrastructure to support several ISA
  • Placeholder for RISC-V implementation
  • Implementation of RISC-V register file

Quality Assurance:

Simulation speed improvements:

  • Cached instruction integration to performance simulation by Pavel Kryukov

New manuals:

External PRs: