Name		Name	Last commit message	Last commit date
Latest commit History 64 Commits
ALU.v		ALU.v
ALU_tb.v		ALU_tb.v
README.md		README.md
basic_units.v		basic_units.v
branch.asm		branch.asm
branch.mem		branch.mem
branch_pred.v		branch_pred.v
cache_wb.v		cache_wb.v
cache_wb_tb.v		cache_wb_tb.v
controller.v		controller.v
controller_tb.v		controller_tb.v
data_memory.v		data_memory.v
data_memory_tb.v		data_memory_tb.v
data_path.v		data_path.v
data_path_tb.v		data_path_tb.v
dotProduct.asm		dotProduct.asm
dotProduct.mem		dotProduct.mem
duel_add.mem		duel_add.mem
duel_branch.asm		duel_branch.asm
duel_branch.mem		duel_branch.mem
forwarding_unit.v		forwarding_unit.v
forwarding_unit_tb.v		forwarding_unit_tb.v
hazard_detector.v		hazard_detector.v
hazard_detector_tb.v		hazard_detector_tb.v
inst_memory.v		inst_memory.v
inst_memory_tb.v		inst_memory_tb.v
multiplier.v		multiplier.v
multiplier_tb.v		multiplier_tb.v
pipeline_stages.v		pipeline_stages.v
program.asm		program.asm
program.mem		program.mem
project 1.docx		project 1.docx
project 2.docx		project 2.docx
project3.docx		project3.docx
project4.docx		project4.docx
reg_file.v		reg_file.v
reg_file_tb.v		reg_file_tb.v

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Superscalar-MIPS

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A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines

processor-architecture mips verilog

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