Single Cycle ARM Processor

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
ALU		ALU
Assembly		Assembly
Instructions		Instructions
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
Arm.sv		Arm.sv
Arm.sv.bak		Arm.sv.bak
README.md		README.md
Single-Cycle-ARM-Processor.qpf		Single-Cycle-ARM-Processor.qpf
Single-Cycle-ARM-Processor.qsf		Single-Cycle-ARM-Processor.qsf
Single-Cycle-ARM-Processor.qws		Single-Cycle-ARM-Processor.qws
Single-Cycle-ARM-Processor_nativelink_simulation.rpt		Single-Cycle-ARM-Processor_nativelink_simulation.rpt
adder.sv		adder.sv
c5_pin_model_dump.txt		c5_pin_model_dump.txt
condcheck.sv		condcheck.sv
condcheck.sv.bak		condcheck.sv.bak
condlogic.sv		condlogic.sv
controller.sv		controller.sv
datapath.sv		datapath.sv
datapath.sv.bak		datapath.sv.bak
decoder.sv		decoder.sv
decoder.sv.bak		decoder.sv.bak
dmem.sv		dmem.sv
extend.sv		extend.sv
extend.sv.bak		extend.sv.bak
flopenr.sv		flopenr.sv
flopenr.sv.bak		flopenr.sv.bak
flopr.sv		flopr.sv
flopr.sv.bak		flopr.sv.bak
imem.sv		imem.sv
imem.sv.bak		imem.sv.bak
memfile.dat		memfile.dat
memfile.hex		memfile.hex
memfile.mem		memfile.mem
memfile.txt		memfile.txt
mux2.sv		mux2.sv
mux2.sv.bak		mux2.sv.bak
processor.sv		processor.sv
processor.sv.bak		processor.sv.bak
processor_testbench.sv		processor_testbench.sv
processor_testbench.sv.bak		processor_testbench.sv.bak
regfile.sv		regfile.sv
regfile.sv.bak		regfile.sv.bak

ErickOF/Single-Cycle-ARM-Processor-FPGA