Work in progress

Name	Statistics		Links
Analog Components	4 / 6
All Digital ICs
Algorithms	4 / 10
GUI - Workbench
Oscilloscope(s)	2 / 3
8085	*
8086
8051
GSM Modem
Verilog
Example Project

######Algorithms

• Expression evaluation using Tree parsing [ WIP ]
• Definitive expression class [ Partially implemented before the start of GSoC, Will need some dusting ]
• Unifying the FSM's currently implemented to provide a reusable custom configurable FPGA-like block to set inputs and get outputs.
• K-Map
• Tree Structure of Connectors
• Auto Updater / Linker Modules
• Espresso algorithm for logic minimization
• Multiplication algos [ Not pushed yet ]
• Division algos
• Caching algos

######Analog Components

• Analog to digital conversion ( 4, 8, 16, IEEE32, IEEE64 )
• Digital to analog conversion ( 4, 8, 16, IEEE32, IEEE64 )
• Analog Buffer Bank ( With attenuation Support )
• Signal Generator - Sine, Square, Ramp, TTL, Triangular
• Resistor, Capacitor, Inductor, Diode
• 555 Timer IC

######ICs

• 7400 Series Completion
• 4000 Series Completion
• Analog To Digital IC
• Digital To Analog IC

WorkBench

• IC tester bench.
• Include docstring support

Oscilloscope(s)

• Simple oscilloscope based on matplotlib
• GUI oscilloscope [ BinPyDesk ]
• ASCII oscilloscope

Microprocessors

• Modules [ WIP ]
• 8085 [ WIP ]
• 8086
• 8051

GSM

• Gsm module capable of communicating with a real GSM Module.

Verilog

• Verilog import
• Verilog export

examples

• IPy Notebook examples for every module. [ Primary version was made. Need to revise to reflect changes to codebase - at end of timeline]
• Sample Project 1
• Sample Project 2