Time-Interleaved-SAR-ADC-Analog-VLSI-Design-Cadence-Virtuoso

This repository is about design and implementation of a time interleaved SAR ADC in Cadence Virtuoso. In this project all the blocks of the ADC is customised and implemented from transistor level itself and no ideal block is used from the libraries of virtuoso. Developed a library for SAR ADC sub-blocks from the transistor level design and simulated a working design of SAR ADC in Cadence virtuoso.