GitHub - 0marAmr/UART-Interface: Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

0marAmr / UART-Interface Public

Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 45 Commits
Shcematics		Shcematics
TBs		TBs
Vivado		Vivado
.gitignore		.gitignore
RX_DATA_SAMPLING.v		RX_DATA_SAMPLING.v
RX_DESERIALIZER.v		RX_DESERIALIZER.v
RX_EDGE_BIT_COUNTER.v		RX_EDGE_BIT_COUNTER.v
RX_FSM.v		RX_FSM.v
RX_PARITY_CHECK.v		RX_PARITY_CHECK.v
RX_START_CHECK.v		RX_START_CHECK.v
RX_STOP_CHECK.v		RX_STOP_CHECK.v
TX_FSM.v		TX_FSM.v
TX_OUTPUT.v		TX_OUTPUT.v
TX_PARITY_CALC.v		TX_PARITY_CALC.v
TX_SERIALIZER.v		TX_SERIALIZER.v
UART.v		UART.v
UART_RX.v		UART_RX.v
UART_TX.v		UART_TX.v