Digital logic design tool and simulator
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Updated
May 28, 2024 - Java
Digital logic design tool and simulator
Composable digital logic simulation in Rust!
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。
This repository contains a vast collection of academic notes, study materials, and resources from various semesters of Datascience course.
CSC302: Digital Logic Design and Analysis [DLDA] & CSL301: Digital System Lab [DS Lab] <Semester III>
A modern hardware definition language and toolchain based on Python
🎓💻All of my projects at University of Tehran
🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the course "Digital Logic Design (EE227)"
My second semester project for my object-oriented programming course. A simulation game for the lab work done in my second semester Digital Logic Design course.
VHDL codes for UART Interface; hardware communication protocol. contains Receiver & Transmitter units & RAM memory.
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
This is a 8 bit binary number multiplier using wallace tree.
A library of useful, fully parameterized RTL designs implemented in SystemVerilog.
This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.
Semester 2 course material for BS Computer Science at Fast National University Of Computer And Emerging Sciences
32-bit Divider circuit implemented using Verilog
Clock and UART Baud rate generation, radix-4 multiplier, function generator & accelerator wrappers.
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