RISCV:fpu_sharing

[SJC0719]

Describe the bug
In the riscv/isr.S file, when the fpu_sharing mode is enabled, to determine whether the exception cause for entering isr_wrapper is triggered by fpu, compare the value of the entire mcause register with 0x2, resulting in failure to enter is_fpu。
The mcause register contains more than just the exception_code field.

To Reproduce

/* determine if this is an Illegal Instruction exception */

csrr t2, mcause

li t1, 2		/* 2 = illegal instruction */

bne t1, t2, no_fp

Expected behavior
exception_code field in register mcause is compared with 0x2 instead of the entire mcause register

/* determine if this is an Illegal Instruction exception */

csrr t2, mcause

and t2, t2, SOC_MCAUSE_EXP_MASK      //The low exception number should be performed or operated on here

li t1, 2		/* 2 = illegal instruction */

bne t1, t2, no_fp

Impact
ztest/fpu_sharing error.

[aescolar]

Duplicate of #72128