I2C in DSP IMX8MP

[mbahmani90]

Hi,

Hope you are all well.

I would like to access i2c peripheral with DSP core. At first I tried to do so by memory mapping but the DSP stops working with the following error:

*** Booting Zephyr OS build v3.6.0-2050-g3c42daee9c1b ***
[00:00:00.002,000] <err> os:  ** FATAL EXCEPTION
[00:00:00.002,000] <err> os:  ** CPU 0 EXCCAUSE 13 (load/store PIF data error)
[00:00:00.002,000] <err> os:  **  PC 0x924014f1 VADDR 0x30a40008
[00:00:00.002,000] <err> os:  **  PS 0x60320
[00:00:00.002,000] <err> os:  **    (INTLEVEL:0 EXCM: 0 UM:1 RING:0 WOE:1 OWB:3 CALLINC:2)
[00:00:00.002,000] <err> os:  **  A0 0x924050a1  SP 0x92409490  A2 0x30a40008  A3 0x92407830
[00:00:00.002,000] <err> os:  **  A4 0x1  A5 0xff  A6 0x1  A7 0x9240addc
[00:00:00.002,000] <err> os:  **  A8 0x92405738  A9 0x92409470 A10 0x9240087c A11 0x9240ac60
[00:00:00.002,000] <err> os:  ** A12 0x9240ac60 A13 0x9240071c A14 0 A15 0x92409460
[00:00:00.002,000] <err> os:  ** LBEG 0x92406944 LEND 0x9240695a LCOUNT 0
[00:00:00.002,000] <err> os:  ** SAR 0x6
[00:00:00.002,000] <err> os:  **  THREADPTR 0x9240068c
[00:00:00.002,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
[00:00:00.002,000] <err> os: Current thread: 0x9240ac60 (unknown)
[00:00:00.107,000] <err> os: Halting system

Then I tried to access I2C registers in Linux as well and I receive "Bus error".

https://community.nxp.com/t5/i-MX-Processors/I2C-issue-IMX8MP/m-p/1856895#M223125

I have check RDC and Clock and test different cases to be able to access I2C registers either Linux or DSP but I couldn't.

I have test GPIO and ECSPI2 by memory mapping and they works well.

Does any one have any specific idea how I am able to access i2c for DSP?
Is there any relevant code in zephyr repository?

[dbaluta]

@mbahmani90 let us get back to you on 8th of May once everyone gets back from Easter holiday!

[mbahmani90]

Many Thanks

[dbaluta]

Can you share some code snippets? Let's first make sure we can access I2C registers from Linux. So let's watch out for clocks, pinctrl, and power domain.

Can you please use NXP memtool instead of devmem? If you have NXP Yocto release there should be a /unit_tests/memtool binary that can access hardware memory.

Then once we can access the memory from Linux we can then try to acess it from the DSP.

@mbahmani90 can you share with us your scenario you want to use the DSP for?

[mbahmani90]

1. In the first step I enabled the I2C3 in imx8mp.dtsi

i2c3: i2c@30a40000 {
	compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x30a40000 0x10000>;
	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	//clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
	clocks = <&clk IMX8MP_SYS_PLL1_160M>;
status = "okay";			
};

2. In imx8mp-evk.dts the pin control has been defined:

&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
}

pinctrl_i2c3: i2c3grp {
fsl,pins = <
		MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2
		MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2
	>;
};

3. Then compiling the Linux and copy and paste the new device tree.
4. Setting the RDC register to 0xFF to be available in all cores:

 devmem2 0x303D0510 w 0x000000FF

5. Enabling the I2C3 clock peripheral based on IMX8MPRM.pdf Page 459, to set SYSTEM_PLL1_DIV5 as clock source with divider 10.

devmem2 0x3038AE00 w 0x1100000A

6. Then when I read I2C3 register (0x30a40000) I receive “Bus error”

  root@imx8mp-lpddr4-evk:~# devmem2 0x30a40000
/dev/mem opened.
[ 5096.664377] audit: type=1701 audit(1678614959.920:16): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=897 comm="devmem2" exe="/usr/bin/devmem2" sig=7 res=1
Memory mapped at address 0xffff940f8000.
Bus error

7. I have also set IOMUXC for I2C SDA and SCL pin (IOMUXC_I2C3_SDA_I2C3_SDA and IOMUXC_I2C3_SCL_I2C3_SCL page 1394 IMX8MPRM.pdf) and I still receive “Bus error”.

devmem2 0x30330210 w 0x00000000
devmem2 0x30330214 w 0x00000000

If any more explanation is required please let me know.

[iuliana-prodan]

Hi @mbahmani90,

What Linux tree are you using?

I've tested on linux-imx (I recommend you to use this one) and, as you can see here for i2c3 you need to enable IMX8MP_CLK_I2C3_ROOT clock.

I've added a hack to have the clock always enabled (made it critical):

git diff
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index f918185a6e9b..01f2f48fbb36 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -673,7 +673,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
        hws[IMX8MP_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0);
        hws[IMX8MP_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0);
        hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
-       hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
+       hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4_flags("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0, CLK_IS_CRITICAL);
        hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);

And, with this change, I can read using memtool:

root@imx8mpevk:~# /unit_tests/memtool -32 0x30a40000 1
E
Reading 0x1 count starting at address 0x30A40000

Bus error (core dumped)
root@imx8mpevk:~# /unit_tests/memtool -16 0x30a40000 1
E
Reading 0x1 count starting at address 0x30A40000

0x30A40000:  0000

root@imx8mpevk:~# /unit_tests/memtool -8 0x30a40000 1
E
Reading 0x1 count starting at address 0x30A40000

0x30A40000:  00

Be aware that I2C Address Register (I2C3_IADR) is 16bits width (see i.MX8MP RM) and only bits 1-7 are used, the others are Reserved:

root@imx8mpevk:~#  /unit_tests/memtool -16 0x30a40000=0x11      
Writing 16-bit value 0x11 to address 0x30A40000
root@imx8mpevk:~#  /unit_tests/memtool -16 0x30a40000 1
E
Reading 0x1 count starting at address 0x30A40000

0x30A40000:  0010

root@imx8mpevk:~# 

[mbahmani90]

Sorry for the delay in response.

Today I applied your advice in Linux environment and it works.

As you mentioned my mistake was on writing/reading 32bits. I had to do so with 16bits.

I will test in DSP and let you soon.

Thank you.

[mbahmani90]

I have tested I2C by DSP and it works well.

#include <stdio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <fsl_clock.h>

#define SLEEP_TIME_MS   1000

int main(void)
{
	uint32_t *i2c3_clk       = ((uint32_t *) 0x3038AE00);
	uint16_t *i2c3_addr      = ((uint16_t *) 0x30A40000);
	uint16_t *i2c3_freq_div  = ((uint16_t *) 0x30A40004);
	uint16_t *i2c3_control   = ((uint16_t *) 0x30A40008);
	uint16_t *i2c3_status    = ((uint16_t *) 0x30A4000C);
	uint16_t *i2c3_io        = ((uint16_t *) 0x30A40010);

	*i2c3_clk = 0x1100000A;
	*i2c3_addr = 0x40;
	*i2c3_control = 0xB0;
	int test_counter = 0;
	while (1) {
		*i2c3_io = test_counter;

		test_counter++;
		if(test_counter >= 256){
			test_counter = 0;
		}
		
		k_msleep(SLEEP_TIME_MS);
	}
}

I am still beginner in Zephyr but it would be possible to modify the code and add it in DSP SDK.

Thanks

[dbaluta]

@mbahmani90 what is your usecase application? What do you want to achieve. We cannot just add random code to zephyr :)

There are several options:

• you have a sensor on i2c then you can use sample/sensor
• If you just want to test the API have a look at zephyr/tests/drivers/i2c